On 07/11/2011 09:18 PM, Jie Zhang wrote:
> OK. There are two parts in your scan chain. Below is my guess:
> It seems IR length of one is 6, the other is 8.
correct
> It seems SIR scans instruction for both parts at once. So it uses length 14.
correct
> So I think it might be a bug in UrJTAG. It should check the total
> length of instruction registers of all parts against the parameter.
> But I don't know what the best fix will be. I took a quick look at the
> svf.c, it seems it only works with scan chain with only one part on
> it. One possible way I think can fix/workaround your issue is to write
> a jtag data file which defines SIR instruction and SDR data register
> properly then tell UrJTAG to use that file for your board, then run
> your SVF file.
I'll write more on this in a separate posting.
> I'm not familiar with SVF at all. So I might be totally wrong.
>
> > One thing I didn't mention in my initial posting is that the 'svf' command
> > produces some warnings
> >
> > Warning svf: command TIR not implemented
> > Warning svf: command TDR not implemented
> > Warning svf: command HIR not implemented
> > Warning svf: command HDR not implemented
> >
> > There are indeed TID, TDR, HIR and HDR commands in the svf file created by
> > the Xilinx impact tools.
> >
> > Is it safe that these svf commands are apparently parsed but ignored ?
> > Is that the reason that jtag gets confused about the IR length ?
> >
> I don't think that's the reason. If the length parameters to them are
> zeros. It should be safe to ignore them.
Some of them have non-zero length, so one wonders why it works
at all. Again, I'll write more on this in a separate posting.
With best regards, Walter
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