On Wed, Feb 8, 2012 at 7:21 PM, <[email protected]> wrote: > Which EJTAG Control Register Fields must be set so that a processor will > enter the debug mode? > > > I tried the following fields of the EJTAG Control Register > PrAcc( bit 18) > ProbEn( bit 15) > ProbTrap( bit 14) > and > EjtagBrk( bit 12) > > but without success. > > > I used a code like this > ... > > set_instr(INSTR_CONTROL);//we want to work with EJTAG Control Register > WriteDataToDataRegister(PrAcc | ProbEn | ProbTrap | EjtagBrk ); > Results=ReadDataFromDataRegister();
I have no idea what these functions are and where they are defined... Can you point us to the implementation of these functions ? > ... > .. > and according EJTAG specification, if CPU entered Debug mode, > DM(bit3) of EJTAG Control Register should be set to 1. > > But when I check Results variable, I can see EjtagBrk( bit 12) is set to 1, > but DM(bit3) is still zero. Maybe you are missing one more set_instr(INSTR_CONTROL); in between write and read ? Still, I have no idea what your functions look like... BR, Drasko ------------------------------------------------------------------------------ Virtualization & Cloud Management Using Capacity Planning Cloud computing makes use of virtualization - but cloud computing also focuses on allowing computing to be delivered as a service. http://www.accelacomm.com/jaw/sfnl/114/51521223/ _______________________________________________ UrJTAG-development mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/urjtag-development
