On Wed, Mar 21, 2018 at 01:47:32PM +0100, Jiri Gaisler wrote:
> On 03/21/2018 11:39 AM, Geert Stappers wrote:
> > means something like "with this patch works 2017.10pre2 for me" ...
>
> Apologies, I am new to this project.
No worries, welcome to UrJTAG
> The 2017.10pre2 works fine for me on Ubuntu 16.04 and 17.10.
Yes!
That is the "go" for 2017.10 \o/
> I'm using FT2232 to access a Xilinx XC6V FPGA
> with libusb-1.0 and libftdi1. The only problem I have is that I cannot
> build UrJTAG in a separate build directory unless I disable the python
> bindings. Building inside the source tree works fine, so it is a minor
> issue:
>
> make[3]: Entering directory
> '/home/jiri/ibm/src/jtag/urjtag/b1/bindings/python'
<snip/>
> make[3]: Leaving directory '/home/jiri/ibm/src/jtag/urjtag/b1/bindings/python'
Please raise that in a fresh thread.
> I have also a patch that adds a bus driver for the AHBJTAG IP core in
> GRLIB (Leon3 open source processor). Should I wait to post this until a
> stable release of UrJTAG has been made ...?
Both choices are fine.
But you are seeking advice:
Wait a few days, so I can focus 2017.10 getting out.
> In addition, I am adding debug support for a RISC-V processor to UrJTAG,
> in the style of what is currently implemented for the Bfin processors.
> Will this be accepted into the project or should I rather make a fork
> and publish it elsewhere?
There is no need for a fork,
because _adding_ doesn't break existing setups.
Groeten
Geert Stappers
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