Hi guys,
To make it clearer, please see attached two commits, one for the
necessary generic updates to allow for the BSDL to be parsed, and
another to add the draft p1020 device support.
Please note that bus support is very draft as explained previously.
Cheers,
Damien
commit a3e6200bc6673601febc11afc08e50d94e3e4fbd
Author: Damien Mascord <tus...@tusker.org>
Date: Mon Sep 21 18:50:21 2020 +1000
Add draft support for Freescale QorIQ P1020
- Adds PART detection for CPU
- Adds initbus support for p1020
diff --git a/urjtag/configure.ac b/urjtag/configure.ac
index 95d1d743..e1a5ae8a 100644
--- a/urjtag/configure.ac
+++ b/urjtag/configure.ac
@@ -637,6 +637,7 @@ URJ_DRIVER_SET([bus], [
mpc824x
mpc8313
mpc837x
+ p1020
ppc405ep
ppc440gx_ebc8
prototype
diff --git a/urjtag/data/Makefile.am b/urjtag/data/Makefile.am
index 7fb82f0f..62e916d7 100644
--- a/urjtag/data/Makefile.am
+++ b/urjtag/data/Makefile.am
@@ -126,6 +126,8 @@ nobase_dist_pkgdata_DATA = \
freescale/mpc8378/mpc8378 \
freescale/mpc8379/STEPPINGS \
freescale/mpc8379/mpc8379 \
+ freescale/p1020/STEPPINGS \
+ freescale/p1020/p1020 \
ibm/PARTS \
ibm/ppc440gx/STEPPINGS \
ibm/ppc440gx/ppc440gx \
diff --git a/urjtag/data/freescale/PARTS b/urjtag/data/freescale/PARTS
index 2f5adc77..eeb7f690 100644
--- a/urjtag/data/freescale/PARTS
+++ b/urjtag/data/freescale/PARTS
@@ -27,5 +27,6 @@
0001100011100100 mpc8378 mpc8378e
0001100011100011 mpc8379 mpc8379
0001100011100010 mpc8379 mpc8379e
+0110100011100010 p1020 p1020
diff --git a/urjtag/data/freescale/p1020/STEPPINGS b/urjtag/data/freescale/p1020/STEPPINGS
new file mode 100644
index 00000000..3d84fc65
--- /dev/null
+++ b/urjtag/data/freescale/p1020/STEPPINGS
@@ -0,0 +1,24 @@
+#
+# $Id: STEPPINGS
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# as published by the Free Software Foundation; either version 2
+# of the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+# 02111-1307, USA.
+#
+# Documentation:
+# [1] Freescale, "Freescale MPC837x Users Guide"
+#
+
+# bits 31-28 of the Device Identification Register
+0000 p1020 0
diff --git a/urjtag/data/freescale/p1020/p1020 b/urjtag/data/freescale/p1020/p1020
new file mode 100644
index 00000000..9d893d86
--- /dev/null
+++ b/urjtag/data/freescale/p1020/p1020
@@ -0,0 +1,1232 @@
+signal XVSS(0)
+signal XVSS(1)
+signal XVSS(2)
+signal XVSS(3)
+signal XVSS(4)
+signal XVSS(5)
+signal XVSS(6)
+signal XVSS(7)
+signal XVDD(0)
+signal XVDD(1)
+signal XVDD(2)
+signal XVDD(3)
+signal XVDD(4)
+signal XVDD(5)
+signal VSS(0)
+signal VSS(1)
+signal VSS(2)
+signal VSS(3)
+signal VSS(4)
+signal VSS(5)
+signal VSS(6)
+signal VSS(7)
+signal VSS(8)
+signal VSS(9)
+signal VSS(10)
+signal VSS(11)
+signal VSS(12)
+signal VSS(13)
+signal VSS(14)
+signal VSS(15)
+signal VSS(16)
+signal VSS(17)
+signal VSS(18)
+signal VSS(19)
+signal VSS(20)
+signal VSS(21)
+signal VSS(22)
+signal VSS(23)
+signal VSS(24)
+signal VSS(25)
+signal VSS(26)
+signal VSS(27)
+signal VSS(28)
+signal VSS(29)
+signal VSS(30)
+signal VSS(31)
+signal VSS(32)
+signal VSS(33)
+signal VSS(34)
+signal VSS(35)
+signal VSS(36)
+signal VSS(37)
+signal VSS(38)
+signal VSS(39)
+signal VSS(40)
+signal VSS(41)
+signal VSS(42)
+signal VSS(43)
+signal VSS(44)
+signal VSS(45)
+signal VSS(46)
+signal VSS(47)
+signal VSS(48)
+signal VSS(49)
+signal VSS(50)
+signal VSS(51)
+signal VSS(52)
+signal VSS(53)
+signal VSS(54)
+signal VSS(55)
+signal VSS(56)
+signal VSS(57)
+signal VSS(58)
+signal VSS(59)
+signal VSS(60)
+signal VSS(61)
+signal VSS(62)
+signal VSS(63)
+signal VSS(64)
+signal VSS(65)
+signal VSS(66)
+signal VSS(67)
+signal VSS(68)
+signal VSS(69)
+signal VSS(70)
+signal VSS(71)
+signal VSS(72)
+signal VSS(73)
+signal VSS(74)
+signal VSS(75)
+signal VSS(76)
+signal VSS(77)
+signal VSS(78)
+signal VSS(79)
+signal VSS(80)
+signal VSS(81)
+signal VSS(82)
+signal VSS(83)
+signal VSS(84)
+signal VSS(85)
+signal VSS(86)
+signal VSS(87)
+signal VSS(88)
+signal VSS(89)
+signal VSS(90)
+signal VSS(91)
+signal VSS(92)
+signal VSS(93)
+signal VSS(94)
+signal VSS(95)
+signal VSS(96)
+signal VSS(97)
+signal VSS(98)
+signal VSS(99)
+signal VSS(100)
+signal VSS(101)
+signal VSS(102)
+signal VSS(103)
+signal VSS(104)
+signal VSS(105)
+signal VSS(106)
+signal VSS(107)
+signal VSS(108)
+signal VSS(109)
+signal VSS(110)
+signal VSS(111)
+signal VSS(112)
+signal VSS(113)
+signal VSS(114)
+signal VSS(115)
+signal VSS(116)
+signal VSS(117)
+signal VSS(118)
+signal VSS(119)
+signal VSS(120)
+signal VSS(121)
+signal VSS(122)
+signal VSS(123)
+signal VSS(124)
+signal VSS(125)
+signal VSS(126)
+signal VSS(127)
+signal VSS(128)
+signal VSS(129)
+signal VSS(130)
+signal VSS(131)
+signal VSS(132)
+signal VSS(133)
+signal VSS(134)
+signal VSS(135)
+signal VSS(136)
+signal VSS(137)
+signal VSS(138)
+signal VSS(139)
+signal VSS(140)
+signal VSS(141)
+signal VSS(142)
+signal VSS(143)
+signal VSS(144)
+signal VSS(145)
+signal VDDC(0)
+signal VDDC(1)
+signal VDDC(2)
+signal VDDC(3)
+signal VDDC(4)
+signal VDDC(5)
+signal VDDC(6)
+signal VDDC(7)
+signal VDDC(8)
+signal VDDC(9)
+signal VDDC(10)
+signal VDDC(11)
+signal VDDC(12)
+signal VDDC(13)
+signal VDDC(14)
+signal VDDC(15)
+signal VDDC(16)
+signal VDDC(17)
+signal VDDC(18)
+signal VDDC(19)
+signal VDDC(20)
+signal VDDC(21)
+signal VDDC(22)
+signal VDDC(23)
+signal VDDC(24)
+signal VDDC(25)
+signal VDDC(26)
+signal VDD(0)
+signal VDD(1)
+signal VDD(2)
+signal VDD(3)
+signal VDD(4)
+signal VDD(5)
+signal VDD(6)
+signal TEMP_CATHODE
+signal TEMP_ANODE
+signal SVSS(0)
+signal SVSS(1)
+signal SVSS(2)
+signal SVSS(3)
+signal SVSS(4)
+signal SVSS(5)
+signal SVSS(6)
+signal SVSS(7)
+signal SVSS(8)
+signal SVSS(9)
+signal SVSS(10)
+signal SVDD(0)
+signal SVDD(1)
+signal SVDD(2)
+signal SVDD(3)
+signal SVDD(4)
+signal SVDD(5)
+signal SENSEVSS
+signal SENSEVDD_RSVD
+signal SENSEVDD
+signal SD_PLL_TPD
+signal SD_PLL_TPA
+signal SD_IMP_CAL_TX
+signal SD_IMP_CAL_RX
+signal SDAVSS
+signal SDAVDD
+signal POVDD
+signal OVDD(0)
+signal OVDD(1)
+signal OVDD(2)
+signal OVDD(3)
+signal OVDD(4)
+signal OVDD(5)
+signal NC(0)
+signal NC(1)
+signal NC(2)
+signal NC(3)
+signal NC(4)
+signal NC(5)
+signal NC(6)
+signal NC(7)
+signal NC(8)
+signal NC(9)
+signal NC(10)
+signal NC(11)
+signal NC(12)
+signal NC(13)
+signal NC(14)
+signal NC(15)
+signal NC(16)
+signal NC(17)
+signal NC(18)
+signal NC(19)
+signal NC(20)
+signal NC(21)
+signal NC(22)
+signal NC(23)
+signal NC(24)
+signal NC(25)
+signal NC(26)
+signal NC(27)
+signal NC(28)
+signal NC(29)
+signal NC(30)
+signal NC(31)
+signal NC(32)
+signal NC(33)
+signal NC(34)
+signal NC(35)
+signal NC(36)
+signal NC(37)
+signal NC(38)
+signal NC(39)
+signal NC(40)
+signal NC(41)
+signal NC(42)
+signal NC(43)
+signal NC(44)
+signal NC(45)
+signal NC(46)
+signal NC(47)
+signal NC(48)
+signal NC(49)
+signal NC(50)
+signal NC(51)
+signal NC(52)
+signal NC(53)
+signal NC(54)
+signal NC(55)
+signal NC(56)
+signal NC(57)
+signal NC(58)
+signal NC(59)
+signal NC(60)
+signal NC(61)
+signal NC(62)
+signal NC(63)
+signal NC(64)
+signal NC(65)
+signal NC(66)
+signal NC(67)
+signal NC(68)
+signal NC(69)
+signal NC(70)
+signal NC(71)
+signal NC(72)
+signal NC(73)
+signal NC(74)
+signal NC(75)
+signal NC(76)
+signal NC(77)
+signal NC(78)
+signal NC(79)
+signal NC(80)
+signal MVREF
+signal LVDD_VSEL
+signal FA_VDD
+signal FA_ANALOG_PIN
+signal FA_ANALOG_G_V
+signal CVDD_VSEL1
+signal CVDD_VSEL0
+signal BVDD_VSEL1
+signal BVDD_VSEL0
+signal AVDD_PLAT
+signal AVDD_DDR
+signal AVDD_CORE1
+signal AVDD_CORE0
+signal USB_STP
+signal USB_PWRFAULT
+signal USB_NXT
+signal USB_DIR
+signal USB_D(0)
+signal USB_D(1)
+signal USB_D(2)
+signal USB_D(3)
+signal USB_D(4)
+signal USB_D(5)
+signal USB_D(6)
+signal USB_D(7)
+signal USB_CLK
+signal UDE1_B
+signal UDE0_B
+signal UART_SOUT(0)
+signal UART_SOUT(1)
+signal UART_SIN01
+signal UART_SIN00
+signal UART_RTS_B(0)
+signal UART_RTS_B(1)
+signal UART_CTS_B01
+signal UART_CTS_B00
+signal TSEC_1588_TRIG_IN2
+signal TSEC_1588_TRIG_IN1
+signal TSEC_1588_PULSE_OUT2
+signal TSEC_1588_PULSE_OUT1
+signal TSEC_1588_CLK_OUT
+signal TSEC_1588_CLK_IN
+signal TSEC_1588_ALARM_OUT2
+signal TSEC_1588_ALARM_OUT1
+signal TSEC2_TX_ER
+signal TSEC2_TXD01
+signal TSEC2_TXD(4)
+signal TSEC2_TXD(5)
+signal TSEC2_CRS
+signal TSEC2_COL
+signal TSEC1_TX_ER
+signal TSEC1_TX_EN
+signal TSEC1_TX_CLK
+signal TSEC1_TXD(0)
+signal TSEC1_TXD(1)
+signal TSEC1_TXD(2)
+signal TSEC1_TXD(3)
+signal TSEC1_TXD(4)
+signal TSEC1_TXD(5)
+signal TSEC1_TXD(6)
+signal TSEC1_TXD(7)
+signal TSEC1_RX_ER
+signal TSEC1_RX_DV
+signal TSEC1_RX_CLK
+signal TSEC1_RXD(0)
+signal TSEC1_RXD(1)
+signal TSEC1_RXD(2)
+signal TSEC1_RXD(3)
+signal TSEC1_RXD(4)
+signal TSEC1_RXD(5)
+signal TSEC1_RXD(6)
+signal TSEC1_RXD(7)
+signal TSEC1_GTX_CLK
+signal TSEC1_CRS
+signal TSEC1_COL
+signal TRST_B
+signal TRIG_OUT
+signal TRIG_IN
+signal TMS
+signal TEST_SEL_B
+signal TDO
+signal TDI
+signal TCK
+signal SYSCLK
+signal SRESET_B
+signal SPI_MOSI
+signal SPI_MISO
+signal SPI_CS3_B
+signal SPI_CS2_B
+signal SPI_CS1_B
+signal SPI_CS0_B
+signal SPI_CLK
+signal SD_TX_B(0)
+signal SD_TX_B(1)
+signal SD_TX_B(2)
+signal SD_TX_B(3)
+signal SD_TX(0)
+signal SD_TX(1)
+signal SD_TX(2)
+signal SD_TX(3)
+signal SD_RX_B(0)
+signal SD_RX_B(1)
+signal SD_RX_B(2)
+signal SD_RX_B(3)
+signal SD_RX(0)
+signal SD_RX(1)
+signal SD_RX(2)
+signal SD_RX(3)
+signal SD_REF_CLK_B
+signal SD_REF_CLK
+signal SDHC_DAT(0)
+signal SDHC_DAT(1)
+signal SDHC_DAT(2)
+signal SDHC_DAT(3)
+signal SDHC_CMD
+signal SDHC_CLK
+signal SCAN_MODE_B
+signal RTC
+signal READY_P1
+signal MWE_B
+signal MSRCID(0)
+signal MSRCID(1)
+signal MSRCID(2)
+signal MSRCID(3)
+signal MSRCID(4)
+signal MRAS_B
+signal MODT(0)
+signal MODT(1)
+signal MECC(0)
+signal MECC(1)
+signal MECC(2)
+signal MECC(3)
+signal MECC(4)
+signal MECC(5)
+signal MECC(6)
+signal MECC(7)
+signal MDVAL
+signal MDQS_B08
+signal MDQS_B(0)
+signal MDQS_B(1)
+signal MDQS_B(2)
+signal MDQS_B(3)
+signal MDQS08
+signal MDQS(0)
+signal MDQS(1)
+signal MDQS(2)
+signal MDQS(3)
+signal MDQ(0)
+signal MDQ(1)
+signal MDQ(2)
+signal MDQ(3)
+signal MDQ(4)
+signal MDQ(5)
+signal MDQ(6)
+signal MDQ(7)
+signal MDQ(8)
+signal MDQ(9)
+signal MDQ(10)
+signal MDQ(11)
+signal MDQ(12)
+signal MDQ(13)
+signal MDQ(14)
+signal MDQ(15)
+signal MDQ(16)
+signal MDQ(17)
+signal MDQ(18)
+signal MDQ(19)
+signal MDQ(20)
+signal MDQ(21)
+signal MDQ(22)
+signal MDQ(23)
+signal MDQ(24)
+signal MDQ(25)
+signal MDQ(26)
+signal MDQ(27)
+signal MDQ(28)
+signal MDQ(29)
+signal MDQ(30)
+signal MDQ(31)
+signal MDM08
+signal MDM(0)
+signal MDM(1)
+signal MDM(2)
+signal MDM(3)
+signal MDIC(0)
+signal MDIC(1)
+signal MCS_B(0)
+signal MCS_B(1)
+signal MCP1_B
+signal MCP0_B
+signal MCK_B(0)
+signal MCK_B(1)
+signal MCK_B(2)
+signal MCK_B(3)
+signal MCKE(0)
+signal MCKE(1)
+signal MCK(0)
+signal MCK(1)
+signal MCK(2)
+signal MCK(3)
+signal MCAS_B
+signal MBA(0)
+signal MBA(1)
+signal MBA(2)
+signal MAPAR_OUT
+signal MAPAR_ERR_B
+signal MA(0)
+signal MA(1)
+signal MA(2)
+signal MA(3)
+signal MA(4)
+signal MA(5)
+signal MA(6)
+signal MA(7)
+signal MA(8)
+signal MA(9)
+signal MA(10)
+signal MA(11)
+signal MA(12)
+signal MA(13)
+signal MA(14)
+signal MA(15)
+signal LWE_B(0)
+signal LWE_B(1)
+signal LSYNC_OUT
+signal LSYNC_IN
+signal LGPL5
+signal LGPL4
+signal LGPL3
+signal LGPL2
+signal LGPL1
+signal LGPL0
+signal LDP(0)
+signal LDP(1)
+signal LCS_B(0)
+signal LCS_B(1)
+signal LCS_B(2)
+signal LCS_B(3)
+signal LCS_B(4)
+signal LCS_B(5)
+signal LCS_B(6)
+signal LCS_B(7)
+signal LCLK(0)
+signal LCLK(1)
+signal LBCTL
+signal LALE
+signal LAD(0)
+signal LAD(1)
+signal LAD(2)
+signal LAD(3)
+signal LAD(4)
+signal LAD(5)
+signal LAD(6)
+signal LAD(7)
+signal LAD(8)
+signal LAD(9)
+signal LAD(10)
+signal LAD(11)
+signal LAD(12)
+signal LAD(13)
+signal LAD(14)
+signal LAD(15)
+signal LA(16)
+signal LA(17)
+signal LA(18)
+signal LA(19)
+signal LA(20)
+signal LA(21)
+signal LA(22)
+signal LA(23)
+signal LA(24)
+signal LA(25)
+signal LA(26)
+signal LA(27)
+signal LA(28)
+signal LA(29)
+signal LA(30)
+signal LA(31)
+signal IRQ_OUT_B
+signal IRQ06
+signal IRQ(0)
+signal IRQ(1)
+signal IRQ(2)
+signal IRQ(3)
+signal IRQ(4)
+signal IRQ(5)
+signal IIC2_SDA
+signal IIC2_SCL
+signal IIC1_SDA
+signal IIC1_SCL
+signal HRESET_REQ_B
+signal HRESET_B
+signal GPIO(0)
+signal GPIO(1)
+signal GPIO(2)
+signal GPIO(3)
+signal GPIO(4)
+signal GPIO(5)
+signal GPIO(6)
+signal GPIO(7)
+signal GPIO(8)
+signal GPIO(9)
+signal GPIO(10)
+signal GPIO(11)
+signal GPIO(12)
+signal GPIO(13)
+signal GPIO(14)
+signal GPIO(15)
+signal EC_MDIO
+signal EC_MDC
+signal EC_GTX_CLK125
+signal DMA2_DREQ_B(0)
+signal DMA2_DDONE_B(0)
+signal DMA2_DACK_B(0)
+signal DMA1_DREQ_B(0)
+signal DMA1_DDONE_B(0)
+signal DMA1_DACK_B(0)
+signal DDRCLK
+signal CLK_OUT
+signal CKSTP_OUT1_B
+signal CKSTP_OUT0_B
+signal CKSTP_IN1_B
+signal CKSTP_IN0_B
+signal ASLEEP
+instruction length 8
+register DIR 32
+register BSR 587
+register BYPASS 1
+instruction PRELOAD 11110000 BSR
+instruction IDCODE 11110011 DIR
+instruction HIGHZ 11110010 BYPASS
+instruction EXTEST 00000000 BSR
+instruction CLAMP 11110001 BYPASS
+instruction SAMPLE/PRELOAD 11110000 BSR
+instruction BYPASS 11111111 BYPASS
+bit 0 C 0 *
+bit 1 B ? EC_MDC 0 0 Z
+bit 2 C 0 *
+bit 3 B ? EC_MDIO 2 0 Z
+bit 4 C 0 *
+bit 5 B ? TSEC_1588_ALARM_OUT1 4 0 Z
+bit 6 O ? *
+bit 7 I ? TSEC_1588_TRIG_IN1
+bit 8 O ? *
+bit 9 I ? TSEC_1588_TRIG_IN2
+bit 10 C 0 *
+bit 11 B ? TSEC_1588_PULSE_OUT2 10 0 Z
+bit 12 O ? *
+bit 13 I ? TSEC_1588_CLK_IN
+bit 14 C 0 *
+bit 15 B ? TSEC_1588_PULSE_OUT1 14 0 Z
+bit 16 C 0 *
+bit 17 B ? TSEC_1588_CLK_OUT 16 0 Z
+bit 18 C 0 *
+bit 19 B ? TSEC1_TXD(4) 18 0 Z
+bit 20 O ? *
+bit 21 I ? TSEC1_RXD(1)
+bit 22 O ? *
+bit 23 I ? TSEC1_RXD(6)
+bit 24 O ? *
+bit 25 I ? TSEC1_RXD(5)
+bit 26 O ? *
+bit 27 I ? TSEC1_RX_ER
+bit 28 C 0 *
+bit 29 B ? TSEC1_TXD(7) 28 0 Z
+bit 30 C 0 *
+bit 31 B ? TSEC1_TX_ER 30 0 Z
+bit 32 O ? *
+bit 33 I ? TSEC1_TX_CLK
+bit 34 O ? *
+bit 35 I ? TSEC1_RXD(7)
+bit 36 C 0 *
+bit 37 B ? TSEC1_TX_EN 36 0 Z
+bit 38 O ? *
+bit 39 I ? TSEC1_RXD(2)
+bit 40 C 0 *
+bit 41 B ? TSEC1_TXD(6) 40 0 Z
+bit 42 O ? *
+bit 43 I ? EC_GTX_CLK125
+bit 44 C 0 *
+bit 45 B ? TSEC1_TXD(3) 44 0 Z
+bit 46 O ? *
+bit 47 I ? TSEC1_RXD(0)
+bit 48 C 0 *
+bit 49 B ? TSEC1_TXD(5) 48 0 Z
+bit 50 O ? *
+bit 51 I ? TSEC1_RX_DV
+bit 52 O ? *
+bit 53 I ? TSEC1_COL
+bit 54 C 0 *
+bit 55 B ? TSEC1_GTX_CLK 54 0 Z
+bit 56 O ? *
+bit 57 I ? TSEC1_RXD(4)
+bit 58 C 0 *
+bit 59 B ? TSEC1_CRS 58 0 Z
+bit 60 O ? *
+bit 61 I ? TSEC1_RXD(3)
+bit 62 C 0 *
+bit 63 B ? TSEC1_TXD(0) 62 0 Z
+bit 64 C 0 *
+bit 65 B ? TSEC1_TXD(1) 64 0 Z
+bit 66 O ? *
+bit 67 I ? TSEC1_RX_CLK
+bit 68 C 0 *
+bit 69 B ? TSEC1_TXD(2) 68 0 Z
+bit 70 C 0 *
+bit 71 B ? TSEC2_TXD(5) 70 0 Z
+bit 72 C 0 *
+bit 73 B ? TSEC2_TXD(4) 72 0 Z
+bit 74 O ? *
+bit 75 I ? TSEC2_CRS
+bit 76 C 0 *
+bit 77 B ? TSEC2_TXD01 76 0 Z
+bit 78 O ? *
+bit 79 I ? TSEC2_COL
+bit 80 C 0 *
+bit 81 B ? TSEC2_TX_ER 80 0 Z
+bit 82 O ? *
+bit 83 I ? TRIG_IN
+bit 84 O ? *
+bit 85 I ? MCP0_B
+bit 86 O ? *
+bit 87 I ? CKSTP_IN1_B
+bit 88 C 0 *
+bit 89 O ? CKSTP_OUT1_B 88 0 Z
+bit 90 O ? *
+bit 91 I ? HRESET_B
+bit 92 O ? *
+bit 93 I ? SRESET_B
+bit 94 C 0 *
+bit 95 B ? READY_P1 94 0 Z
+bit 96 O ? *
+bit 97 I ? CKSTP_IN0_B
+bit 98 C 0 *
+bit 99 O ? CKSTP_OUT0_B 98 0 Z
+bit 100 C 0 *
+bit 101 B ? DMA1_DREQ_B(0) 100 0 Z
+bit 102 C 0 *
+bit 103 B ? DMA2_DDONE_B(0) 102 0 Z
+bit 104 C 0 *
+bit 105 B ? DMA2_DREQ_B(0) 104 0 Z
+bit 106 O ? *
+bit 107 I ? SYSCLK
+bit 108 C 0 *
+bit 109 B ? ASLEEP 108 0 Z
+bit 110 C 0 *
+bit 111 O ? CLK_OUT 110 0 Z
+bit 112 C 0 *
+bit 113 B ? DMA1_DDONE_B(0) 112 0 Z
+bit 114 C 0 *
+bit 115 B ? HRESET_REQ_B 114 0 Z
+bit 116 C 0 *
+bit 117 B ? TRIG_OUT 116 0 Z
+bit 118 C 0 *
+bit 119 B ? GPIO(4) 118 0 Z
+bit 120 C 0 *
+bit 121 B ? DMA1_DACK_B(0) 120 0 Z
+bit 122 C 0 *
+bit 123 B ? DMA2_DACK_B(0) 122 0 Z
+bit 124 C 0 *
+bit 125 B ? GPIO(0) 124 0 Z
+bit 126 C 0 *
+bit 127 B ? GPIO(5) 126 0 Z
+bit 128 C 0 *
+bit 129 B ? MSRCID(1) 128 0 Z
+bit 130 C 0 *
+bit 131 B ? GPIO(6) 130 0 Z
+bit 132 C 0 *
+bit 133 B ? GPIO(2) 132 0 Z
+bit 134 C 0 *
+bit 135 B ? GPIO(1) 134 0 Z
+bit 136 C 0 *
+bit 137 B ? GPIO(7) 136 0 Z
+bit 138 C 0 *
+bit 139 B ? MSRCID(2) 138 0 Z
+bit 140 C 0 *
+bit 141 B ? MSRCID(0) 140 0 Z
+bit 142 C 0 *
+bit 143 B ? MSRCID(3) 142 0 Z
+bit 144 O ? *
+bit 145 I ? IRQ(3)
+bit 146 C 0 *
+bit 147 B ? GPIO(3) 146 0 Z
+bit 148 C 0 *
+bit 149 B ? MSRCID(4) 148 0 Z
+bit 150 C 0 *
+bit 151 O ? IRQ_OUT_B 150 0 Z
+bit 152 C 0 *
+bit 153 B ? MDVAL 152 0 Z
+bit 154 O ? *
+bit 155 I ? MCP1_B
+bit 156 O ? *
+bit 157 I ? IRQ(5)
+bit 158 O ? *
+bit 159 I ? IRQ(4)
+bit 160 O ? *
+bit 161 I ? IRQ(1)
+bit 162 C 0 *
+bit 163 B ? IRQ06 162 0 Z
+bit 164 O ? *
+bit 165 I ? IRQ(0)
+bit 166 O ? *
+bit 167 I ? IRQ(2)
+bit 168 O ? *
+bit 169 I ? RTC
+bit 170 O ? *
+bit 171 I ? UDE1_B
+bit 172 O ? *
+bit 173 I ? UDE0_B
+bit 174 C 0 *
+bit 175 B ? UART_SOUT(1) 174 0 Z
+bit 176 C 0 *
+bit 177 B ? UART_RTS_B(1) 176 0 Z
+bit 178 C 0 *
+bit 179 B ? UART_SOUT(0) 178 0 Z
+bit 180 C 0 *
+bit 181 B ? UART_CTS_B01 180 0 Z
+bit 182 O ? *
+bit 183 I ? UART_CTS_B00
+bit 184 C 0 *
+bit 185 B ? UART_RTS_B(0) 184 0 Z
+bit 186 O ? *
+bit 187 I ? UART_SIN00
+bit 188 C 0 *
+bit 189 B ? UART_SIN01 188 0 Z
+bit 190 C 0 *
+bit 191 B ? IIC2_SCL 190 0 Z
+bit 192 C 0 *
+bit 193 B ? IIC2_SDA 192 0 Z
+bit 194 C 0 *
+bit 195 B ? IIC1_SDA 194 0 Z
+bit 196 C 0 *
+bit 197 B ? IIC1_SCL 196 0 Z
+bit 198 C 0 *
+bit 199 B ? SDHC_DAT(2) 198 0 Z
+bit 200 C 0 *
+bit 201 B ? SDHC_DAT(3) 200 0 Z
+bit 202 C 0 *
+bit 203 B ? SDHC_DAT(0) 202 0 Z
+bit 204 C 0 *
+bit 205 B ? SDHC_CLK 204 0 Z
+bit 206 C 0 *
+bit 207 B ? SDHC_DAT(1) 206 0 Z
+bit 208 C 0 *
+bit 209 B ? SDHC_CMD 208 0 Z
+bit 210 O ? *
+bit 211 I ? SPI_MISO
+bit 212 C 0 *
+bit 213 B ? SPI_CS2_B 212 0 Z
+bit 214 C 0 *
+bit 215 B ? SPI_CS1_B 214 0 Z
+bit 216 C 0 *
+bit 217 B ? SPI_CS3_B 216 0 Z
+bit 218 C 0 *
+bit 219 B ? SPI_CS0_B 218 0 Z
+bit 220 C 0 *
+bit 221 B ? SPI_MOSI 220 0 Z
+bit 222 C 0 *
+bit 223 B ? SPI_CLK 222 0 Z
+bit 224 O ? *
+bit 225 I ? USB_CLK
+bit 226 C 0 *
+bit 227 B ? USB_PWRFAULT 226 0 Z
+bit 228 C 0 *
+bit 229 B ? USB_STP 228 0 Z
+bit 230 C 0 *
+bit 231 B ? USB_D(7) 230 0 Z
+bit 232 C 0 *
+bit 233 B ? USB_D(3) 232 0 Z
+bit 234 C 0 *
+bit 235 B ? USB_D(0) 234 0 Z
+bit 236 C 0 *
+bit 237 B ? USB_D(5) 236 0 Z
+bit 238 C 0 *
+bit 239 B ? USB_DIR 238 0 Z
+bit 240 C 0 *
+bit 241 B ? USB_D(6) 240 0 Z
+bit 242 C 0 *
+bit 243 B ? USB_D(2) 242 0 Z
+bit 244 C 0 *
+bit 245 B ? USB_NXT 244 0 Z
+bit 246 C 0 *
+bit 247 B ? USB_D(1) 246 0 Z
+bit 248 C 0 *
+bit 249 B ? USB_D(4) 248 0 Z
+bit 250 C 0 *
+bit 251 B ? GPIO(15) 250 0 Z
+bit 252 C 0 *
+bit 253 B ? GPIO(14) 252 0 Z
+bit 254 C 0 *
+bit 255 B ? GPIO(13) 254 0 Z
+bit 256 C 0 *
+bit 257 B ? GPIO(11) 256 0 Z
+bit 258 C 0 *
+bit 259 B ? GPIO(10) 258 0 Z
+bit 260 C 0 *
+bit 261 B ? GPIO(12) 260 0 Z
+bit 262 C 0 *
+bit 263 B ? GPIO(8) 262 0 Z
+bit 264 C 0 *
+bit 265 B ? GPIO(9) 264 0 Z
+bit 266 C 0 *
+bit 267 B ? LA(19) 266 0 Z
+bit 268 C 0 *
+bit 269 B ? LA(31) 268 0 Z
+bit 270 C 0 *
+bit 271 B ? LA(23) 270 0 Z
+bit 272 C 0 *
+bit 273 B ? LA(30) 272 0 Z
+bit 274 C 0 *
+bit 275 B ? LA(29) 274 0 Z
+bit 276 C 0 *
+bit 277 B ? LA(24) 276 0 Z
+bit 278 C 0 *
+bit 279 B ? LA(28) 278 0 Z
+bit 280 C 0 *
+bit 281 B ? LA(26) 280 0 Z
+bit 282 C 0 *
+bit 283 B ? LAD(8) 282 0 Z
+bit 284 C 0 *
+bit 285 B ? LA(25) 284 0 Z
+bit 286 C 0 *
+bit 287 B ? LA(17) 286 0 Z
+bit 288 C 0 *
+bit 289 B ? LCS_B(3) 288 0 Z
+bit 290 C 0 *
+bit 291 B ? LA(27) 290 0 Z
+bit 292 C 0 *
+bit 293 B ? LA(16) 292 0 Z
+bit 294 C 0 *
+bit 295 B ? LAD(1) 294 0 Z
+bit 296 C 0 *
+bit 297 B ? LA(18) 296 0 Z
+bit 298 C 0 *
+bit 299 B ? LA(21) 298 0 Z
+bit 300 C 0 *
+bit 301 B ? LCS_B(0) 300 0 Z
+bit 302 C 0 *
+bit 303 B ? LAD(3) 302 0 Z
+bit 304 C 0 *
+bit 305 B ? LGPL2 304 0 Z
+bit 306 C 0 *
+bit 307 B ? LCS_B(2) 306 0 Z
+bit 308 C 0 *
+bit 309 B ? LAD(7) 308 0 Z
+bit 310 C 0 *
+bit 311 B ? LBCTL 310 0 Z
+bit 312 C 0 *
+bit 313 B ? LAD(4) 312 0 Z
+bit 314 C 0 *
+bit 315 B ? LDP(0) 314 0 Z
+bit 316 C 0 *
+bit 317 B ? LGPL5 316 0 Z
+bit 318 C 0 *
+bit 319 B ? LSYNC_OUT 318 0 Z
+bit 320 C 0 *
+bit 321 B ? LDP(1) 320 0 Z
+bit 322 C 0 *
+bit 323 B ? LAD(12) 322 0 Z
+bit 324 C 0 *
+bit 325 B ? LAD(2) 324 0 Z
+bit 326 C 0 *
+bit 327 B ? LSYNC_IN 326 0 Z
+bit 328 C 0 *
+bit 329 B ? LAD(0) 328 0 Z
+bit 330 C 0 *
+bit 331 B ? LAD(5) 330 0 Z
+bit 332 C 0 *
+bit 333 B ? LALE 332 0 Z
+bit 334 C 0 *
+bit 335 B ? LAD(6) 334 0 Z
+bit 336 C 0 *
+bit 337 B ? LCS_B(7) 336 0 Z
+bit 338 C 0 *
+bit 339 B ? LAD(10) 338 0 Z
+bit 340 C 0 *
+bit 341 B ? LAD(14) 340 0 Z
+bit 342 C 0 *
+bit 343 B ? LAD(15) 342 0 Z
+bit 344 C 0 *
+bit 345 B ? LCS_B(5) 344 0 Z
+bit 346 C 0 *
+bit 347 B ? LCLK(0) 346 0 Z
+bit 348 C 0 *
+bit 349 B ? LCLK(1) 348 0 Z
+bit 350 C 0 *
+bit 351 B ? LAD(11) 350 0 Z
+bit 352 C 0 *
+bit 353 B ? LCS_B(6) 352 0 Z
+bit 354 C 0 *
+bit 355 B ? LGPL1 354 0 Z
+bit 356 C 0 *
+bit 357 B ? LGPL4 356 0 Z
+bit 358 C 0 *
+bit 359 B ? LA(20) 358 0 Z
+bit 360 C 0 *
+bit 361 B ? LCS_B(1) 360 0 Z
+bit 362 C 0 *
+bit 363 B ? LWE_B(0) 362 0 Z
+bit 364 C 0 *
+bit 365 B ? LGPL0 364 0 Z
+bit 366 C 0 *
+bit 367 B ? LCS_B(4) 366 0 Z
+bit 368 C 0 *
+bit 369 B ? LWE_B(1) 368 0 Z
+bit 370 C 0 *
+bit 371 B ? LA(22) 370 0 Z
+bit 372 C 0 *
+bit 373 B ? LAD(13) 372 0 Z
+bit 374 C 0 *
+bit 375 B ? LAD(9) 374 0 Z
+bit 376 C 0 *
+bit 377 B ? LGPL3 376 0 Z
+bit 378 C 0 *
+bit 379 B ? MDIC(1) 378 0 Z
+bit 380 C 0 *
+bit 381 B ? MDIC(0) 380 0 Z
+bit 382 O ? *
+bit 383 O ? *
+bit 384 C 0 *
+bit 385 O ? MCK(2) 384 0 Z
+bit 386 C 0 *
+bit 387 O ? MODT(1) 386 0 Z
+bit 388 C 0 *
+bit 389 B ? MA(13) 388 0 Z
+bit 390 C 0 *
+bit 391 O ? MCS_B(1) 390 0 Z
+bit 392 C 0 *
+bit 393 O ? MCS_B(0) 392 0 Z
+bit 394 C 0 *
+bit 395 B ? MCAS_B 394 0 Z
+bit 396 C 0 *
+bit 397 O ? MODT(0) 396 0 Z
+bit 398 C 0 *
+bit 399 O ? MWE_B 398 0 Z
+bit 400 C 0 *
+bit 401 B ? MA(10) 400 0 Z
+bit 402 C 0 *
+bit 403 O ? MRAS_B 402 0 Z
+bit 404 C 0 *
+bit 405 B ? MA(0) 404 0 Z
+bit 406 C 0 *
+bit 407 B ? MBA(0) 406 0 Z
+bit 408 C 0 *
+bit 409 B ? MBA(1) 408 0 Z
+bit 410 C 0 *
+bit 411 B ? MA(2) 410 0 Z
+bit 412 C 0 *
+bit 413 B ? MA(4) 412 0 Z
+bit 414 C 0 *
+bit 415 B ? MA(1) 414 0 Z
+bit 416 C 0 *
+bit 417 B ? MA(5) 416 0 Z
+bit 418 C 0 *
+bit 419 B ? MA(6) 418 0 Z
+bit 420 C 0 *
+bit 421 B ? MA(9) 420 0 Z
+bit 422 C 0 *
+bit 423 B ? MA(8) 422 0 Z
+bit 424 C 0 *
+bit 425 B ? MAPAR_OUT 424 0 Z
+bit 426 O ? *
+bit 427 I ? MAPAR_ERR_B
+bit 428 O ? *
+bit 429 O ? *
+bit 430 C 0 *
+bit 431 O ? MCK(3) 430 0 Z
+bit 432 O ? *
+bit 433 O ? *
+bit 434 C 0 *
+bit 435 O ? MCK(0) 434 0 Z
+bit 436 C 0 *
+bit 437 B ? MA(12) 436 0 Z
+bit 438 C 0 *
+bit 439 B ? MA(3) 438 0 Z
+bit 440 C 0 *
+bit 441 B ? MA(7) 440 0 Z
+bit 442 C 0 *
+bit 443 B ? MBA(2) 442 0 Z
+bit 444 C 0 *
+bit 445 B ? MA(14) 444 0 Z
+bit 446 C 0 *
+bit 447 B ? MA(11) 446 0 Z
+bit 448 C 0 *
+bit 449 B ? MA(15) 448 0 Z
+bit 450 C 0 *
+bit 451 O ? MCKE(1) 450 0 Z
+bit 452 C 0 *
+bit 453 O ? MCKE(0) 452 0 Z
+bit 454 C 0 *
+bit 455 B ? MECC(2) 454 0 Z
+bit 456 C 0 *
+bit 457 B ? MECC(7) 456 0 Z
+bit 458 C 0 *
+bit 459 B ? MECC(6) 458 0 Z
+bit 460 C 0 *
+bit 461 B ? MDQS08 460 0 Z
+bit 462 O ? *
+bit 463 O ? *
+bit 464 C 0 *
+bit 465 B ? MDM08 464 0 Z
+bit 466 C 0 *
+bit 467 B ? MECC(3) 466 0 Z
+bit 468 C 0 *
+bit 469 B ? MECC(1) 468 0 Z
+bit 470 C 0 *
+bit 471 B ? MECC(0) 470 0 Z
+bit 472 C 0 *
+bit 473 B ? MECC(4) 472 0 Z
+bit 474 C 0 *
+bit 475 B ? MECC(5) 474 0 Z
+bit 476 C 0 *
+bit 477 B ? MDQ(27) 476 0 Z
+bit 478 C 0 *
+bit 479 B ? MDM(3) 478 0 Z
+bit 480 C 0 *
+bit 481 B ? MDQ(26) 480 0 Z
+bit 482 C 0 *
+bit 483 B ? MDQ(31) 482 0 Z
+bit 484 C 0 *
+bit 485 B ? MDQS(3) 484 0 Z
+bit 486 O ? *
+bit 487 O ? *
+bit 488 C 0 *
+bit 489 B ? MDQ(25) 488 0 Z
+bit 490 C 0 *
+bit 491 B ? MDQ(28) 490 0 Z
+bit 492 C 0 *
+bit 493 B ? MDQ(30) 492 0 Z
+bit 494 C 0 *
+bit 495 B ? MDQ(29) 494 0 Z
+bit 496 C 0 *
+bit 497 B ? MDQ(24) 496 0 Z
+bit 498 C 0 *
+bit 499 B ? MDQ(18) 498 0 Z
+bit 500 C 0 *
+bit 501 B ? MDQ(19) 500 0 Z
+bit 502 C 0 *
+bit 503 B ? MDQ(23) 502 0 Z
+bit 504 C 0 *
+bit 505 B ? MDQ(22) 504 0 Z
+bit 506 O ? *
+bit 507 O ? *
+bit 508 C 0 *
+bit 509 B ? MDQS(2) 508 0 Z
+bit 510 C 0 *
+bit 511 B ? MDM(2) 510 0 Z
+bit 512 C 0 *
+bit 513 B ? MDQ(17) 512 0 Z
+bit 514 C 0 *
+bit 515 B ? MDQ(21) 514 0 Z
+bit 516 C 0 *
+bit 517 B ? MDQ(16) 516 0 Z
+bit 518 C 0 *
+bit 519 B ? MDQ(20) 518 0 Z
+bit 520 C 0 *
+bit 521 B ? MDQ(14) 520 0 Z
+bit 522 C 0 *
+bit 523 B ? MDQ(11) 522 0 Z
+bit 524 C 0 *
+bit 525 B ? MDQ(15) 524 0 Z
+bit 526 C 0 *
+bit 527 B ? MDQ(10) 526 0 Z
+bit 528 C 0 *
+bit 529 B ? MDQS(1) 528 0 Z
+bit 530 O ? *
+bit 531 O ? *
+bit 532 C 0 *
+bit 533 B ? MDM(1) 532 0 Z
+bit 534 C 0 *
+bit 535 B ? MDQ(8) 534 0 Z
+bit 536 C 0 *
+bit 537 B ? MDQ(9) 536 0 Z
+bit 538 C 0 *
+bit 539 B ? MDQ(12) 538 0 Z
+bit 540 C 0 *
+bit 541 B ? MDQ(13) 540 0 Z
+bit 542 O ? *
+bit 543 O ? *
+bit 544 C 0 *
+bit 545 O ? MCK(1) 544 0 Z
+bit 546 C 0 *
+bit 547 B ? MDQ(3) 546 0 Z
+bit 548 C 0 *
+bit 549 B ? MDQ(2) 548 0 Z
+bit 550 C 0 *
+bit 551 B ? MDQ(7) 550 0 Z
+bit 552 C 0 *
+bit 553 B ? MDQ(6) 552 0 Z
+bit 554 C 0 *
+bit 555 B ? MDQS(0) 554 0 Z
+bit 556 O ? *
+bit 557 O ? *
+bit 558 C 0 *
+bit 559 B ? MDM(0) 558 0 Z
+bit 560 C 0 *
+bit 561 B ? MDQ(1) 560 0 Z
+bit 562 C 0 *
+bit 563 B ? MDQ(0) 562 0 Z
+bit 564 C 0 *
+bit 565 B ? MDQ(5) 564 0 Z
+bit 566 C 0 *
+bit 567 B ? MDQ(4) 566 0 Z
+bit 568 O ? *
+bit 569 I ? DDRCLK
+bit 570 I ? SD_RX(0)
+bit 571 C 1 *
+bit 572 O 0 SD_TX(0) 571 1 Z
+bit 573 C 1 *
+bit 574 O 0 SD_TX(1) 573 1 Z
+bit 575 I ? SD_RX(1)
+bit 576 I ? SD_REF_CLK
+bit 577 O ? *
+bit 578 O ? *
+bit 579 I ? SD_RX(2)
+bit 580 C 1 *
+bit 581 O 0 SD_TX(2) 580 1 Z
+bit 582 C 1 *
+bit 583 O 0 SD_TX(3) 582 1 Z
+bit 584 I ? SD_RX(3)
+bit 585 C 0 *
+bit 586 B ? TSEC_1588_ALARM_OUT2 585 0 Z
diff --git a/urjtag/src/bus/Makefile.am b/urjtag/src/bus/Makefile.am
index 3a082439..3fc9c265 100644
--- a/urjtag/src/bus/Makefile.am
+++ b/urjtag/src/bus/Makefile.am
@@ -122,6 +122,10 @@ if ENABLE_BUS_MPC837X
libbus_la_SOURCES += mpc837x.c
endif
+if ENABLE_BUS_P1020
+libbus_la_SOURCES += p1020.c
+endif
+
if ENABLE_BUS_PPC405EP
libbus_la_SOURCES += ppc405ep.c
endif
diff --git a/urjtag/src/bus/buses_list.h b/urjtag/src/bus/buses_list.h
index aaaacc91..87728ef9 100644
--- a/urjtag/src/bus/buses_list.h
+++ b/urjtag/src/bus/buses_list.h
@@ -98,6 +98,9 @@ _URJ_BUS(mpc8313)
#ifdef ENABLE_BUS_MPC837X
_URJ_BUS(mpc837x)
#endif
+#ifdef ENABLE_BUS_P1020
+_URJ_BUS(p1020)
+#endif
#ifdef ENABLE_BUS_PPC405EP
_URJ_BUS(ppc405ep)
#endif
diff --git a/urjtag/src/bus/p1020.c b/urjtag/src/bus/p1020.c
new file mode 100644
index 00000000..fcf4564d
--- /dev/null
+++ b/urjtag/src/bus/p1020.c
@@ -0,0 +1,515 @@
+/*
+ * Freescale P1020 compatible bus driver via BSR
+ * Copyright (C) 2010 Andrzej Jalowiecki, Damien Mascord
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ * 02111-1307, USA.
+ *
+ *
+ * Documentation:
+ * [1] Freescale, "Freescale P1020 Reference Manual"
+ *
+ */
+
+#include "sysdep.h"
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <urjtag/chain.h>
+#include <urjtag/part.h>
+#include <urjtag/bus.h>
+#include <urjtag/bssignal.h>
+
+#include "buses.h"
+#include "generic_bus.h"
+
+#define LBC_NUM_LCS 8
+#define LBC_NUM_LWE 2
+#define LBC_NUM_LAD 16
+#define LBC_NUM_LA 16
+
+typedef struct {
+ uint32_t last_adr;
+ urj_part_signal_t *nlcs[LBC_NUM_LCS];
+ urj_part_signal_t *lad[LBC_NUM_LAD];
+ urj_part_signal_t *la[LBC_NUM_LA];
+ urj_part_signal_t *nlwe[LBC_NUM_LWE];
+ urj_part_signal_t *nloe;
+ urj_part_signal_t *ale;
+ urj_part_signal_t *lbctl;
+ int lbc_muxed;
+ int lbc_num_ad;
+ int lbc_num_d;
+} bus_params_t;
+
+#define LAST_ADR ((bus_params_t *) bus->params)->last_adr /* Last used address */
+#define nCS ((bus_params_t *) bus->params)->nlcs /* Chipselect# */
+#define nWE ((bus_params_t *) bus->params)->nlwe /* Write enable# */
+#define nOE ((bus_params_t *) bus->params)->nloe /* Output enable# */
+#define ALE ((bus_params_t *) bus->params)->ale /* Addres strobe */
+#define BCTL ((bus_params_t *) bus->params)->lbctl /* Write /Read# */
+
+#define LAD ((bus_params_t *) bus->params)->lad /* Addres/Data Bus Mux */
+#define LA ((bus_params_t *) bus->params)->la /* Addres Bus nonMux */
+
+/**
+ * bus->driver->(*new_bus)
+ *
+ */
+static urj_bus_t *
+p1020_bus_new (urj_chain_t *chain, const urj_bus_driver_t *driver,
+ const urj_param_t *cmd_params[])
+{
+ urj_bus_t *bus;
+ bus_params_t *bp;
+ urj_part_t *part;
+ char buff[10];
+ int i;
+ int failed = 0;
+
+ bus = urj_bus_generic_new (chain, driver, sizeof (bus_params_t));
+ if (bus == NULL)
+ return NULL;
+
+ part = bus->part;
+ bp = bus->params;
+
+ /* default values */
+ bp->lbc_muxed = 0;
+ bp->lbc_num_d = 8;
+ bp->lbc_num_ad = 25;
+
+ for (i = 0; cmd_params[i] != NULL; i++)
+ {
+ switch (cmd_params[i]->key)
+ {
+ case URJ_BUS_PARAM_KEY_HELP:
+ urj_bus_generic_free (bus);
+ urj_log (URJ_LOG_LEVEL_NORMAL,
+ _("Usage: initbus p1020 [mux] [width=WIDTH]\n"
+ " MUX multiplexed data bus (default no)\n"
+ " WIDTH data bus width - 8, 16, 32 (default 8)\n"));
+ return NULL;
+ case URJ_BUS_PARAM_KEY_MUX:
+ bp->lbc_muxed = 1;
+ break;
+ case URJ_BUS_PARAM_KEY_WIDTH:
+ switch (cmd_params[i]->value.lu)
+ {
+ case 8:
+ bp->lbc_num_d = 8;
+ break;
+ case 16:
+ bp->lbc_num_d = 16;
+ break;
+ case 32:
+ bp->lbc_num_d = 32;
+ break;
+ default:
+ urj_error_set (URJ_ERROR_UNSUPPORTED,
+ _(" Only 8, 16, 32 bus width are suported\n"));
+ }
+ break;
+ default:
+ urj_bus_generic_free (bus);
+ urj_error_set (URJ_ERROR_SYNTAX, "unrecognised bus parameter '%s'",
+ urj_param_string (&urj_bus_param_list, cmd_params[i]));
+ return NULL;
+ }
+ }
+
+ if (!bp->lbc_muxed && (bp->lbc_num_d > 16))
+ {
+ urj_bus_generic_free (bus);
+ urj_error_set (URJ_ERROR_UNSUPPORTED,
+ _(" Only 8 and 16 non multiplexed bus width are suported\n"));
+ return NULL;
+ }
+
+ if (bp->lbc_muxed)
+ bp->lbc_num_ad = LBC_NUM_LAD;
+
+ /* Get the signals */
+ /*if (bp->lbc_muxed)
+ {
+ failed |= urj_bus_generic_attach_sig (part, &(ALE), "LALE");
+ for (i = 0; i < LBC_NUM_LAD; i++)
+ {
+ sprintf (buff, "LAD(%d)", i);
+ failed |= urj_bus_generic_attach_sig (part, &(LAD[i]), buff);
+ }
+ }
+ else
+ {
+ failed |= urj_bus_generic_attach_sig (part, &(LA[7]), "LDP(0)");
+ failed |= urj_bus_generic_attach_sig (part, &(LA[8]), "LDP(1)");
+ failed |= urj_bus_generic_attach_sig (part, &(LA[9]), "LGPL5");
+ failed |= urj_bus_generic_attach_sig (part, &(LA[10]), "LALE");
+ for (i = 11; i < LBC_NUM_LAD - 5; i++)
+ {
+ sprintf (buff, "LAD(%d)", i + 5);
+ failed |= urj_bus_generic_attach_sig (part, &(LA[i]), buff);
+ }
+ }*/
+
+ for (i = 0; i < LBC_NUM_LAD; i++)
+ {
+ sprintf (buff, "LAD(%d)", i);
+ failed |= urj_bus_generic_attach_sig (part, &(LAD[i]), buff);
+ }
+
+ for (i = 0; i < LBC_NUM_LA; i++)
+ {
+ sprintf (buff, "LA(%d)", i + LBC_NUM_LAD);
+ failed |= urj_bus_generic_attach_sig (part, &(LA[i]), buff);
+ }
+
+ for (i = 0; i < LBC_NUM_LCS; i++)
+ {
+ sprintf (buff, "LCS_B(%d)", i);
+ failed |= urj_bus_generic_attach_sig (part, &(nCS[i]), buff);
+ }
+
+ for (i = 0; i < LBC_NUM_LWE; i++)
+ {
+ sprintf (buff, "LWE_B(%d)", i);
+ failed |= urj_bus_generic_attach_sig (part, &(nWE[i]), buff);
+ }
+
+ failed |= urj_bus_generic_attach_sig (part, &(nOE), "LGPL2");
+ failed |= urj_bus_generic_attach_sig (part, &(BCTL), "LBCTL");
+
+ if (failed)
+ {
+ urj_bus_generic_free (bus);
+ return NULL;
+ }
+
+ urj_log (URJ_LOG_LEVEL_NORMAL,
+ "%sMUXed %db address, %db data bus\n",
+ ((bp->lbc_muxed) ? "" : "Non-"),
+ bp->lbc_num_ad, bp->lbc_num_d);
+
+ return bus;
+}
+
+/**
+ * bus->driver->(*printinfo)
+ *
+ */
+static void
+p1020_bus_printinfo (urj_log_level_t ll, urj_bus_t *bus)
+{
+ int i;
+
+ for (i = 0; i < bus->chain->parts->len; i++)
+ if (bus->part == bus->chain->parts->parts[i])
+ break;
+ urj_log (ll, _("Freescale p1020 compatible bus driver via BSR (JTAG part No. %d)\n"), i);
+}
+
+/**
+ * bus->driver->(*area)
+ *
+ */
+static int
+p1020_bus_area (urj_bus_t *bus, uint32_t adr, urj_bus_area_t *area)
+{
+ bus_params_t *bp = bus->params;
+
+ area->description = N_("Local Bus Controller");
+ area->start = UINT32_C(0x00000000);
+ area->length = UINT64_C(0x100000000);
+ area->width = bp->lbc_num_d;
+ return URJ_STATUS_OK;
+}
+
+static void
+setup_address (urj_bus_t *bus, uint32_t a)
+{
+ bus_params_t *bp = bus->params;
+ urj_part_t *p = bus->part;
+ int i;
+
+ if (bp->lbc_muxed)
+ {
+ for (i = 0; i < bp->lbc_num_ad; i++)
+ urj_part_set_signal (p, LAD[LBC_NUM_LAD - i - 1], 1, (a >> i) & 1);
+
+ for (i = 0; i < LBC_NUM_LA; i++)
+ urj_part_set_signal (p, LA[LBC_NUM_LA - i - 1], 1, (a >> i) & 1);
+ }
+ else
+ {
+ for (i = 0; i < LBC_NUM_LA; i++)
+ urj_part_set_signal (p, LA[LBC_NUM_LA - i - 1], 1, (a >> i) & 1);
+ }
+}
+
+static void
+set_data_in (urj_bus_t *bus, uint32_t adr)
+{
+ bus_params_t *bp = bus->params;
+ urj_part_t *p = bus->part;
+ urj_bus_area_t area;
+ int i;
+
+ p1020_bus_area (bus, adr, &area);
+ if (area.width > bp->lbc_num_d)
+ return;
+
+ for (i = 0; i < area.width; i++)
+ urj_part_set_signal_input (p, LAD[bp->lbc_num_d - i - 1]);
+}
+
+static void
+setup_data (urj_bus_t *bus, uint32_t adr, uint32_t d)
+{
+ bus_params_t *bp = bus->params;
+ urj_part_t *p = bus->part;
+ urj_bus_area_t area;
+ int i;
+
+ p1020_bus_area (bus, adr, &area);
+ if (area.width > bp->lbc_num_d)
+ return;
+
+ for (i = 0; i < area.width; i++)
+ urj_part_set_signal (p, LAD[bp->lbc_num_d - i - 1], 1, (d >> i) & 1);
+}
+
+static uint32_t
+get_data (urj_bus_t *bus, uint32_t adr)
+{
+ bus_params_t *bp = bus->params;
+ urj_part_t *p = bus->part;
+ urj_bus_area_t area;
+ uint32_t d = 0;
+ int i;
+
+ p1020_bus_area (bus, adr, &area);
+ if (area.width > bp->lbc_num_d)
+ return 0;
+
+ for (i = 0; i < area.width; i++)
+ d |= (urj_part_get_signal (p, LAD[bp->lbc_num_d - i - 1]) << i);
+ return d;
+}
+
+/**
+ * bus->driver->(*read_start)
+ *
+ */
+static int
+p1020_bus_read_start (urj_bus_t *bus, uint32_t adr)
+{
+ bus_params_t *bp = bus->params;
+ urj_chain_t *chain = bus->chain;
+ urj_part_t *p = bus->part;
+ uint8_t cs;
+ int i;
+
+ LAST_ADR = adr;
+ cs = 0;
+
+ for (i = 0; i < LBC_NUM_LCS; i++)
+ urj_part_set_signal (p, nCS[i], 1, !(cs == i));
+
+ for (i = 0; i < LBC_NUM_LWE; i++)
+ urj_part_set_signal_high (p, nWE[i]);
+
+ setup_address (bus, adr);
+
+ if (bp->lbc_muxed)
+ {
+ urj_part_set_signal_high (p, BCTL); /* Address Out */
+ urj_part_set_signal_high (p, ALE);
+ urj_part_set_signal_high (p, nOE);
+ urj_tap_chain_shift_data_registers (chain, 0);
+ urj_part_set_signal_low (p, BCTL); /* Data In */
+ urj_part_set_signal_low (p, ALE);
+ urj_part_set_signal_low (p, nOE);
+ }
+ else
+ {
+ urj_part_set_signal_low (p, BCTL); /* Data In */
+ urj_part_set_signal_low (p, nOE);
+ set_data_in (bus, adr);
+ }
+
+ urj_tap_chain_shift_data_registers (chain, 0);
+
+ return URJ_STATUS_OK;
+}
+
+/**
+ * bus->driver->(*read_next)
+ *
+ */
+static uint32_t
+p1020_bus_read_next (urj_bus_t *bus, uint32_t adr)
+{
+ bus_params_t *bp = bus->params;
+ urj_chain_t *chain = bus->chain;
+ urj_part_t *p = bus->part;
+ uint32_t d;
+
+ if (bp->lbc_muxed)
+ {
+ set_data_in (bus, adr);
+ urj_tap_chain_shift_data_registers (chain, 0);
+
+ urj_tap_chain_shift_data_registers (chain, 1);
+ d = get_data (bus, LAST_ADR);
+
+ setup_address (bus, adr);
+ LAST_ADR = adr;
+
+ urj_part_set_signal_high (p, BCTL); /* Address Out */
+ urj_part_set_signal_high (p, ALE);
+ urj_part_set_signal_high (p, nOE);
+ urj_tap_chain_shift_data_registers (chain, 0);
+
+ urj_part_set_signal_low (p, BCTL); /* Data In */
+ urj_part_set_signal_low (p, ALE);
+ urj_part_set_signal_low (p, nOE);
+ urj_tap_chain_shift_data_registers (chain, 0);
+ }
+ else
+ {
+ setup_address (bus, adr); /* Data In */
+ urj_tap_chain_shift_data_registers (chain, 1);
+ d = get_data (bus, LAST_ADR);
+ }
+
+ LAST_ADR = adr;
+ return d;
+}
+
+/**
+ * bus->driver->(*read_end)
+ *
+ */
+static uint32_t
+p1020_bus_read_end (urj_bus_t *bus)
+{
+ bus_params_t *bp = bus->params;
+ urj_chain_t *chain = bus->chain;
+ urj_part_t *p = bus->part;
+ int i;
+
+ if (bp->lbc_muxed)
+ {
+ set_data_in (bus, LAST_ADR);
+ urj_tap_chain_shift_data_registers (chain, 0);
+ urj_part_set_signal_high (p, ALE);
+ }
+
+ for (i = 0; i < LBC_NUM_LCS; i++)
+ urj_part_set_signal_high (p, nCS[i]);
+
+ urj_part_set_signal_high (p, BCTL);
+ urj_part_set_signal_high (p, nOE);
+
+ urj_tap_chain_shift_data_registers (chain, 1);
+
+ return get_data (bus, LAST_ADR);
+}
+
+/**
+ * bus->driver->(*write)
+ *
+ */
+static void
+p1020_bus_write (urj_bus_t *bus, uint32_t adr, uint32_t data)
+{
+ bus_params_t *bp = bus->params;
+ urj_chain_t *chain = bus->chain;
+ urj_part_t *p = bus->part;
+ urj_bus_area_t area;
+ uint8_t cs;
+ int i;
+
+ p1020_bus_area (bus, adr, &area);
+ if (area.width > bp->lbc_num_d)
+ return;
+
+ cs = 0;
+ urj_part_set_signal_high (p, BCTL);
+ urj_part_set_signal_high (p, nOE);
+
+ for (i = 0; i < LBC_NUM_LWE; i++)
+ urj_part_set_signal_high (p, nWE[i]);
+
+ if (bp->lbc_muxed)
+ {
+ setup_address (bus, adr);
+ urj_part_set_signal_high (p, ALE);
+ urj_tap_chain_shift_data_registers (chain, 0);
+ urj_part_set_signal_low (p, ALE);
+ urj_tap_chain_shift_data_registers (chain, 0);
+ }
+ else
+ setup_address (bus, adr);
+
+ for (i = 0; i < LBC_NUM_LCS; i++)
+ urj_part_set_signal (p, nCS[i], 1, !(cs == i));
+
+ setup_data (bus, adr, data);
+
+ urj_tap_chain_shift_data_registers (chain, 0);
+
+ switch (area.width)
+ {
+ case 32:
+ urj_part_set_signal_low (p, nWE[3]);
+ urj_part_set_signal_low (p, nWE[2]);
+ case 16:
+ urj_part_set_signal_low (p, nWE[1]);
+ case 8:
+ urj_part_set_signal_low (p, nWE[0]);
+ default:
+ break;
+ }
+
+ urj_tap_chain_shift_data_registers (chain, 0);
+
+ for (i = 0; i < LBC_NUM_LWE; i++)
+ urj_part_set_signal_high (p, nWE[i]);
+
+ urj_tap_chain_shift_data_registers (chain, 0);
+}
+
+const urj_bus_driver_t urj_bus_p1020_bus = {
+ "p1020",
+ N_("Freescale p1020 compatible bus driver via BSR, parameter: [mux] [width]"),
+ p1020_bus_new,
+ urj_bus_generic_free,
+ p1020_bus_printinfo,
+ urj_bus_generic_prepare_extest,
+ p1020_bus_area,
+ p1020_bus_read_start,
+ p1020_bus_read_next,
+ p1020_bus_read_end,
+ urj_bus_generic_read,
+ urj_bus_generic_write_start,
+ p1020_bus_write,
+ urj_bus_generic_no_init,
+ urj_bus_generic_no_enable,
+ urj_bus_generic_no_disable,
+ URJ_BUS_TYPE_PARALLEL,
+};
commit a65c1a2ac1db8537837372edc933fe9ff09271f8
Author: Damien Mascord <tus...@tusker.org>
Date: Mon Sep 21 18:51:54 2020 +1000
Update BSDL support to allow to parse MPC85xx and P1020 BSDL
- main change is in relation to PORT_GROUPING
diff --git a/urjtag/data/bsdl/STD_1149_1_2001 b/urjtag/data/bsdl/STD_1149_1_2001
index a0e1c3e0..21a82f18 100644
--- a/urjtag/data/bsdl/STD_1149_1_2001
+++ b/urjtag/data/bsdl/STD_1149_1_2001
@@ -1,259 +1,173 @@
---
--- $Id$
---
--- Email header accompanying the original Yacc code:
--- http://www.eda.org/vug_bbs/bsdl.parser
---
--- -----------------------------------8<--------------------------------------
---
--- Hello All,
---
--- This is this first mailing of the BSDL* Version 0.0 parser specifications
--- we are sending to people who request it from our publicized E-Mail address;
---
--- bsdl%hpm...@hplabs.hp.com
---
--- You are free to redistribute this at will, but we feel that it would be
--- better if respondents asked for it directly so that their addresses can
--- be entered into our list for future mailings and updates.
---
--- It would be helpful if you could confirm receipt of this transmission.
--- We also would be very interested to hear about your experiences with this
--- information and what you are planning to do with BSDL.
---
--- Regards,
---
--- Ken Parker
--- Hewlett-Packard Company
---
---
--- *Boundary-Scan Description Language - as documented in:
---
--- "A Language for Describing Boundary-Scan Devices", K.P. Parker
--- and S. Oresjo, Proceedings 1990 International Test Conference,
--- Washington DC, pp 222-234
---
---
--- - -----------------cut here---------------------------------------------------
---
---
--- 901004.0721 Hewlett-Packard Company
--- 901016.1049 Manufacturing Test Division
--- P.O. Box 301
--- Loveland, Colorado 80537
--- USA
---
--- October 1990
--- Hello BSDL Parser Requestor,
---
--- This Electronic Mail reply contains the computer specifications for
--- Hewlett-Packard's Version 0.0 BSDL parser. This section of the reply
--- explains the contents of the rest of this file.
---
--- This file is composed of seven (7) parts:
---
--- 1) How to use this file
---
--- 2) UNIX* Lex source (lexicographical tokenizing rules)
---
--- 3) UNIX* Yacc source (BNF-like syntax description)
---
--- 4) A sample main program to recognize BSDL.
---
--- 5) A BSDL description of the Texas Instruments 74bct8374 that is
--- recognized by the parser, for testing purposes.
---
--- 6) The VHDL package STD_1149_1_1990 needed by this parser.
---
--- 7) [added 901016] Porting experiences to other systems.
---
---
--- RECOMMENDATION: Save a copy of this file in archival storage before
--- processing it via the instructions below. This will
--- allow you to recover from errors, and allow you to
--- compare subsequently released data for changes.
---
--- DISCLAIMERS:
---
--- 1. The IEEE 1149.1 Working Group has not endorsed BSDL Version 0.0 and
--- therefore no person may represent it as an IEEE standard or imply that
--- a resulting IEEE standard will be identical to it.
---
--- 2. The IEEE 1149.1 Working Group recognizes that BSDL Version 0.0 is a
--- well-conceived initiative that is likely to excelerate the creation
--- of tools that support the 1149.1 standard. As such, changes and
--- enhancements will be carefully considered so as not to needlessly
--- disrupt these development efforts. The overriding goal is the
--- ultimate success of the 1149.1 standard.
---
--- LEGAL NOTICES:
---
--- Hewlett-Packard Company makes no warranty of any kind with regard to
--- this information, including, but not limited to, the implied
--- waranties of merchantability and fitness for a particular purpose.
---
--- Hewlett-Packard Company shall not be liable for errors contained
--- herein or direct, indirect, special, incidental, or consequential
--- damages in connection with the furnishing, performance, or use of
--- this material.
---
---
--- *UNIX is a trademark of AT&T in the USA and other countries.
---
-
--- STD_1149_1_1990 VHDL Package and Package Body in support of
--- BSDL Version 0.0
---
-
--- package STD_1149_1_1990 is -- Created 900525
- package STD_1149_1_2001 is
-
- -- Give pin mapping declarations
-
- attribute PIN_MAP : string;
- subtype PIN_MAP_STRING is string;
-
- -- Give TAP control declarations
-
- type CLOCK_LEVEL is (LOW, BOTH);
- type CLOCK_INFO is record
- FREQ : real;
- LEVEL: CLOCK_LEVEL;
- end record;
-
- attribute TAP_SCAN_IN : boolean;
- attribute TAP_SCAN_OUT : boolean;
- attribute TAP_SCAN_CLOCK: CLOCK_INFO;
- attribute TAP_SCAN_MODE : boolean;
- attribute TAP_SCAN_RESET: boolean;
-
- -- Give instruction register declarations
-
- attribute INSTRUCTION_LENGTH : integer;
- attribute INSTRUCTION_OPCODE : string;
- attribute INSTRUCTION_CAPTURE : string;
- attribute INSTRUCTION_DISABLE : string;
- attribute INSTRUCTION_GUARD : string;
- attribute INSTRUCTION_PRIVATE : string;
- attribute INSTRUCTION_USAGE : string;
- attribute INSTRUCTION_SEQUENCE : string;
-
- -- Give ID and USER code declarations
-
- type ID_BITS is ('0', '1', 'x', 'X');
- type ID_STRING is array (31 downto 0) of ID_BITS;
- attribute IDCODE_REGISTER : ID_STRING;
- attribute USERCODE_REGISTER: ID_STRING;
-
- -- Give register declarations
-
- attribute REGISTER_ACCESS : string;
-
- -- Give boundary cell declarations
-
- type BSCAN_INST is (EXTEST, SAMPLE, INTEST, RUNBIST);
- type CELL_TYPE is (INPUT, INTERNAL, CLOCK,
- CONTROL, CONTROLR, OUTPUT2,
- OUTPUT3, BIDIR_IN, BIDIR_OUT);
- type CAP_DATA is (PI, PO, UPD, CAP, X, ZERO, ONE);
- type CELL_DATA is record
- CT : CELL_TYPE;
- I : BSCAN_INST;
- CD : CAP_DATA;
- end record;
- type CELL_INFO is array (positive range <>) of CELL_DATA;
-
- -- Boundary Cell defered constants (see package body)
-
- constant BC_1 : CELL_INFO;
- constant BC_2 : CELL_INFO;
- constant BC_3 : CELL_INFO;
- constant BC_4 : CELL_INFO;
- constant BC_5 : CELL_INFO;
- constant BC_6 : CELL_INFO;
-
- -- Boundary Register declarations
-
- attribute BOUNDARY_CELLS : string;
- attribute BOUNDARY_LENGTH : integer;
- attribute BOUNDARY_REGISTER : string;
-
- -- Miscellaneous
-
- attribute DESIGN_WARNING : string;
---end STD_1149_1_1990; -- End of 1149.1-1990 Package
-end STD_1149_1_2001;
-
-
---package body STD_1149_1_1990 is -- Standard Boundary Cells
- -- Written 900525
-package body STD_1149_1_2001 is
-
--- Description for f10-12, f10-16, f10-18c, f10-18d, f10-21c
-
-constant BC_1 : CELL_INFO :=
- ((INPUT, EXTEST, PI), (OUTPUT2, EXTEST, PI),
- (INPUT, SAMPLE, PI), (OUTPUT2, SAMPLE, PI),
- (INPUT, INTEST, PI), (OUTPUT2, INTEST, PI),
- (INPUT, RUNBIST, PI), (OUTPUT2, RUNBIST, PI),
- (OUTPUT3, EXTEST, PI), (INTERNAL, EXTEST, PI),
- (OUTPUT3, SAMPLE, PI), (INTERNAL, SAMPLE, PI),
- (OUTPUT3, INTEST, PI), (INTERNAL, INTEST, PI),
- (OUTPUT3, RUNBIST, PI), (INTERNAL, RUNBIST, PI),
- (CONTROL, EXTEST, PI), (CONTROLR, EXTEST, PI),
- (CONTROL, SAMPLE, PI), (CONTROLR, SAMPLE, PI),
- (CONTROL, INTEST, PI), (CONTROLR, INTEST, PI),
- (CONTROL, RUNBIST, PI), (CONTROLR, RUNBIST, PI) );
-
--- Description for f10-8, f10-17, f10-19c, f10-19d, f10-22c
-
-constant BC_2 : CELL_INFO :=
- ((INPUT, EXTEST, PI), (OUTPUT2, EXTEST, UPD),
- (INPUT, SAMPLE, PI), (OUTPUT2, SAMPLE, PI),
- (INPUT, INTEST, UPD), -- Intest on output2 not supported
- (INPUT, RUNBIST, UPD), (OUTPUT2, RUNBIST, UPD),
- (OUTPUT3, EXTEST, UPD), (INTERNAL, EXTEST, PI),
- (OUTPUT3, SAMPLE, PI), (INTERNAL, SAMPLE, PI),
- (OUTPUT3, INTEST, PI), (INTERNAL, INTEST, UPD),
- (OUTPUT3, RUNBIST, PI), (INTERNAL, RUNBIST, UPD),
- (CONTROL, EXTEST, UPD), (CONTROLR, EXTEST, UPD),
- (CONTROL, SAMPLE, PI), (CONTROLR, SAMPLE, PI),
- (CONTROL, INTEST, PI), (CONTROLR, INTEST, PI),
- (CONTROL, RUNBIST, PI), (CONTROLR, RUNBIST, PI) );
-
--- Description for f10-9
-
-constant BC_3 : CELL_INFO :=
- ((INPUT, EXTEST, PI), (INTERNAL, EXTEST, PI),
- (INPUT, SAMPLE, PI), (INTERNAL, SAMPLE, PI),
- (INPUT, INTEST, PI), (INTERNAL, INTEST, PI),
- (INPUT, RUNBIST, PI), (INTERNAL, RUNBIST, PI) );
-
--- Description for f10-10, f10-11
-
-constant BC_4 : CELL_INFO :=
- ((INPUT, EXTEST, PI), -- Intest on input not supported
- (INPUT, SAMPLE, PI), -- Runbist on input not supported
- (CLOCK, EXTEST, PI), (INTERNAL, EXTEST, PI),
- (CLOCK, SAMPLE, PI), (INTERNAL, SAMPLE, PI),
- (CLOCK, INTEST, PI), (INTERNAL, INTEST, PI),
- (CLOCK, RUNBIST, PI), (INTERNAL, RUNBIST, PI) );
-
--- Description for f10-20c, a combined Input/Control
-
-constant BC_5 : CELL_INFO :=
- ((INPUT, EXTEST, PI), (CONTROL, EXTEST, PI),
- (INPUT, SAMPLE, PI), (CONTROL, SAMPLE, PI),
- (INPUT, INTEST, UPD), (CONTROL, INTEST, UPD),
- (INPUT, RUNBIST, PI), (CONTROL, RUNBIST, PI) );
-
--- Description for f10-22d, a reversible cell
-
-constant BC_6 : CELL_INFO :=
- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, UPD),
- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
- (BIDIR_IN, INTEST, UPD), (BIDIR_OUT, INTEST, PI),
- (BIDIR_IN, RUNBIST, UPD), (BIDIR_OUT, RUNBIST, PI) );
-
---end STD_1149_1_1990; -- End of 1149.1-1990 Package Body
-end STD_1149_1_2001;
+ package STD_1149_1_2001 is
+ -- Give component conformance declaration
+ attribute COMPONENT_CONFORMANCE : string;
+
+ -- Give pin mapping declarations
+ attribute PIN_MAP : string;
+ subtype PIN_MAP_STRING is string;
+
+ -- Give TAP control declarations
+ type CLOCK_LEVEL is (LOW, BOTH);
+ type CLOCK_INFO is record
+ FREQ : real;
+ LEVEL: CLOCK_LEVEL;
+ end record;
+
+ attribute TAP_SCAN_IN : boolean;
+ attribute TAP_SCAN_OUT : boolean;
+ attribute TAP_SCAN_CLOCK: CLOCK_INFO;
+ attribute TAP_SCAN_MODE : boolean;
+ attribute TAP_SCAN_RESET: boolean;
+ -- Give instruction register declarations
+ attribute INSTRUCTION_LENGTH : integer;
+ attribute INSTRUCTION_OPCODE : string;
+ attribute INSTRUCTION_CAPTURE : string;
+ attribute INSTRUCTION_PRIVATE : string;
+
+ -- Give ID and USER code declarations
+ type ID_BITS is ('0', '1', 'x', 'X');
+ type ID_STRING is array (31 downto 0) of ID_BITS;
+ attribute IDCODE_REGISTER : ID_STRING;
+ attribute USERCODE_REGISTER: ID_STRING;
+
+ -- Give register declarations
+ attribute REGISTER_ACCESS : string;
+
+ -- Give boundary cell declarations
+ type BSCAN_INST is (EXTEST, SAMPLE, INTEST);
+ type CELL_TYPE is (INPUT, INTERNAL, CLOCK, OBSERVE_ONLY,
+ CONTROL, CONTROLR, OUTPUT2,
+ OUTPUT3, BIDIR_IN, BIDIR_OUT);
+ type CAP_DATA is (PI, PO, UPD, CAP, X, ZERO, ONE);
+ type CELL_DATA is record
+ CT : CELL_TYPE;
+ I : BSCAN_INST;
+ CD : CAP_DATA;
+ end record;
+ type CELL_INFO is array (positive range <>) of CELL_DATA;
+
+ -- Boundary cell deferred constants (see package body)
+ constant BC_0 : CELL_INFO;
+ constant BC_1 : CELL_INFO;
+ constant BC_2 : CELL_INFO;
+ constant BC_3 : CELL_INFO;
+ constant BC_4 : CELL_INFO;
+ constant BC_5 : CELL_INFO;
+ constant BC_6 : CELL_INFO;
+ constant BC_7 : CELL_INFO;
+ constant BC_8 : CELL_INFO;
+ constant BC_9 : CELL_INFO;
+ constant BC_10 : CELL_INFO;
+ -- Boundary register declarations
+ attribute BOUNDARY_LENGTH : integer;
+ attribute BOUNDARY_REGISTER : string;
+
+ -- Miscellaneous
+ attribute PORT_GROUPING : string;
+ attribute RUNBIST_EXECUTION : string;
+ attribute INTEST_EXECUTION : string;
+ subtype BSDL_EXTENSION is string;
+ attribute COMPLIANCE_PATTERNS : string;
+ attribute DESIGN_WARNING : string;
+
+ end STD_1149_1_2001; -- End of 1149.1-2001 Package
+
+ package body STD_1149_1_2001 is -- Standard boundary cells
+
+ -- Generic cell capturing minimum allowed data
+ constant BC_0 : CELL_INFO :=
+ ((INPUT, EXTEST, PI), (OUTPUT2, EXTEST, X),
+ (INPUT, SAMPLE, PI), (OUTPUT2, SAMPLE, PI),
+ (INPUT, INTEST, X), (OUTPUT2, INTEST, PI),
+ (OUTPUT3, EXTEST, X), (INTERNAL, EXTEST, X),
+ (OUTPUT3, SAMPLE, PI), (INTERNAL, SAMPLE, X),
+ (OUTPUT3, INTEST, PI), (INTERNAL, INTEST, X),
+ (CONTROL, EXTEST, X), (CONTROLR, EXTEST, X),
+ (CONTROL, SAMPLE, PI), (CONTROLR, SAMPLE, PI),
+ (CONTROL, INTEST, PI), (CONTROLR, INTEST, PI),
+ (BIDIR_IN,EXTEST, PI), (BIDIR_OUT, EXTEST, X ),
+ (BIDIR_IN,SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
+ (BIDIR_IN,INTEST, X ), (BIDIR_OUT, INTEST, PI),
+ (OBSERVE_ONLY, SAMPLE, PI), (OBSERVE_ONLY, EXTEST, PI) );
+
+ -- Description for f11-18, f11-30, f11-34c, f11-34d, f11-36c, f11-46d
+ constant BC_1 : CELL_INFO :=
+ ((INPUT, EXTEST, PI), (OUTPUT2, EXTEST, PI),
+ (INPUT, SAMPLE, PI), (OUTPUT2, SAMPLE, PI),
+ (INPUT, INTEST, PI), (OUTPUT2, INTEST, PI),
+ (OUTPUT3, EXTEST, PI), (INTERNAL, EXTEST, PI),
+ (OUTPUT3, SAMPLE, PI), (INTERNAL, SAMPLE, PI),
+ (OUTPUT3, INTEST, PI), (INTERNAL, INTEST, PI),
+ (CONTROL, EXTEST, PI), (CONTROLR, EXTEST, PI),
+ (CONTROL, SAMPLE, PI), (CONTROLR, SAMPLE, PI),
+ (CONTROL, INTEST, PI), (CONTROLR, INTEST, PI) );
+
+ -- Description for f11-14, f11-31, f11-35c, f11-35d, f11-37c,
+ -- f11-38c, f11-39(output) and f11-41c
+ constant BC_2 : CELL_INFO :=
+ ((INPUT, EXTEST, PI), (OUTPUT2, EXTEST, UPD),
+ (INPUT, SAMPLE, PI), (OUTPUT2, SAMPLE, PI),
+ (INPUT, INTEST, UPD), -- Intest on output2 not supported
+ (OUTPUT3, EXTEST, UPD), (INTERNAL, EXTEST, PI),
+ (OUTPUT3, SAMPLE, PI), (INTERNAL, SAMPLE, PI),
+ (OUTPUT3, INTEST, PI), (INTERNAL, INTEST, UPD),
+ (CONTROL, EXTEST, UPD), (CONTROLR, EXTEST, UPD),
+ (CONTROL, SAMPLE, PI), (CONTROLR, SAMPLE, PI),
+ (CONTROL, INTEST, PI), (CONTROLR, INTEST, PI) );
+
+ -- Description for f11-15
+ constant BC_3 : CELL_INFO :=
+ ((INPUT, EXTEST, PI), (INTERNAL, EXTEST, PI),
+ (INPUT, SAMPLE, PI), (INTERNAL, SAMPLE, PI),
+ (INPUT, INTEST, PI), (INTERNAL, INTEST, PI) );
+
+ -- Description for f11-16, f11-17, f11-39(input)
+ constant BC_4 : CELL_INFO :=
+ ((INPUT, EXTEST, PI), -- Intest on input not supported
+ (INPUT, SAMPLE, PI),
+ (OBSERVE_ONLY, EXTEST, PI),
+ (OBSERVE_ONLY, SAMPLE, PI), -- Intest on observe_only not supported
+ (CLOCK, EXTEST, PI), (INTERNAL, EXTEST, PI),
+ (CLOCK, SAMPLE, PI), (INTERNAL, SAMPLE, PI),
+ (CLOCK, INTEST, PI), (INTERNAL, INTEST, PI) );
+
+ -- Description for f11-46c, a combined input/control
+ constant BC_5 : CELL_INFO :=
+ ((INPUT, EXTEST, PI), (CONTROL, EXTEST, PI),
+ (INPUT, SAMPLE, PI), (CONTROL, SAMPLE, PI),
+ (INPUT, INTEST, UPD), (CONTROL, INTEST, UPD) );
+
+ -- Description for f11-38d, a reversible cell
+ -- !! Not recommended; replaced by BC_7 below !!
+ constant BC_6 : CELL_INFO :=
+ ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, UPD),
+ (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
+ (BIDIR_IN, INTEST, UPD), (BIDIR_OUT, INTEST, PI) );
+
+ -- Description for f11-37d, self monitor reversible
+ -- !! Recommended over cell BC_6 !!
+ constant BC_7 : CELL_INFO :=
+ ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PO),
+ (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
+ (BIDIR_IN, INTEST, UPD), (BIDIR_OUT, INTEST, PI) );
+
+ -- Description for 11-40, f11-41d
+ constant BC_8 : CELL_INFO :=
+ -- Intest on bidir not supported
+ ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PO),
+ (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PO) );
+
+ -- Description for f11-32
+ constant BC_9 : CELL_INFO :=
+ -- Self-monitoring output that supports Intest
+ ((OUTPUT2, EXTEST, PO), (OUTPUT3, EXTEST, PO),
+ (OUTPUT2, SAMPLE, PI), (OUTPUT3, SAMPLE, PI),
+ (OUTPUT2, INTEST, PI), (OUTPUT3, INTEST, PI) );
+
+ -- Description for f11-33
+ constant BC_10 : CELL_INFO :=
+ -- Self-monitoring output that does not support Intest
+ ((OUTPUT2, EXTEST, PO), (OUTPUT3, EXTEST, PO),
+ (OUTPUT2, SAMPLE, PO), (OUTPUT3, SAMPLE, PO) );
+
+ end STD_1149_1_2001; -- End of IEEE Std 1149.1-2001 Package Body
diff --git a/urjtag/src/bsdl/bsdl_bison.y b/urjtag/src/bsdl/bsdl_bison.y
index c00d3fd7..6f7be147 100644
--- a/urjtag/src/bsdl/bsdl_bison.y
+++ b/urjtag/src/bsdl/bsdl_bison.y
@@ -192,6 +192,7 @@ void yyerror (urj_bsdl_parser_priv_t *, const char *);
%token CONSTANT PIN_MAP
+%token PORT_GROUPING DIFFERENTIAL_CURRENT DIFFERENTIAL_VOLTAGE
%token PHYSICAL_PIN_MAP PIN_MAP_STRING
%token TAP_SCAN_IN TAP_SCAN_OUT TAP_SCAN_MODE TAP_SCAN_RESET
%token TAP_SCAN_CLOCK
@@ -239,6 +240,8 @@ void yyerror (urj_bsdl_parser_priv_t *, const char *);
%type <integer> Disable_Value
%type <str> Standard_Reg
%type <str> Instruction_Name
+%type <str> Port_Grouping_Type
+%type <str> Port_Grouping
%start BSDL_Statement
@@ -258,6 +261,7 @@ BSDL_Statement : BSDL_Pin_Map
| BSDL_Inst_Guard
| BSDL_Inst_Private
| BSDL_Idcode_Register
+ | BSDL_Port_Grouping
| BSDL_Usercode_Register
| BSDL_Register_Access
| BSDL_Boundary_Length
@@ -388,6 +392,31 @@ BSDL_Idcode_Register : IDCODE_REGISTER BIN_X_PATTERN
{ priv_data->jtag_ctrl->idcode = $2; }
;
+/****************************************************************************/
+BSDL_Port_Grouping : PORT_GROUPING Port_Grouping_Mapping
+;
+
+Port_Grouping_Mapping : IDENTIFIER LPAREN Port_Grouping_List RPAREN
+;
+
+Port_Grouping_Type : DIFFERENTIAL_VOLTAGE
+ | DIFFERENTIAL_CURRENT
+;
+
+Port_Grouping_List : LPAREN Port_Grouping RPAREN
+ | Port_Grouping_List COMMA LPAREN Port_Grouping RPAREN
+ | error
+ {
+ Print_Error (priv_data, _("Error in Port Grouping List"));
+ BUMP_ERROR;
+ YYABORT;
+ }
+;
+Port_Grouping : IDENTIFIER LPAREN DECIMAL_NUMBER RPAREN COMMA IDENTIFIER LPAREN DECIMAL_NUMBER RPAREN
+ | IDENTIFIER COMMA IDENTIFIER
+ { free ($1); }
+;
+
/****************************************************************************/
BSDL_Usercode_Register : USERCODE_REGISTER BIN_X_PATTERN
{ priv_data->jtag_ctrl->usercode = $2; }
diff --git a/urjtag/src/bsdl/bsdl_flex.l b/urjtag/src/bsdl/bsdl_flex.l
index 1f7b98c9..6fc50859 100644
--- a/urjtag/src/bsdl/bsdl_flex.l
+++ b/urjtag/src/bsdl/bsdl_flex.l
@@ -209,6 +209,7 @@ Boundary_Length BOUNDARY_LENGTH
Boundary_Register BOUNDARY_REGISTER
Idcode_Register IDCODE_REGISTER
Usercode_Register USERCODE_REGISTER
+Port_Grouping PORT_GROUPING
Boundary BOUNDARY
Bypass BYPASS
Clamp CLAMP
@@ -278,6 +279,7 @@ Recommended RECOMMENDED
ISC_Illegal_Exit ISC_ILLEGAL_EXIT
%%
{Constant} {yyextra->Base = DECIMAL; return( CONSTANT ); }
+{Port_Grouping} {return( PORT_GROUPING ); }
{Pin_Map} {return( PIN_MAP ); }
{Physical_Pin_Map} {return( PHYSICAL_PIN_MAP ); }
{Pin_Map_String} {return( PIN_MAP_STRING ); }
diff --git a/urjtag/src/bsdl/bsdl_types.h b/urjtag/src/bsdl/bsdl_types.h
index efe09579..44fe8f50 100644
--- a/urjtag/src/bsdl/bsdl_types.h
+++ b/urjtag/src/bsdl/bsdl_types.h
@@ -144,6 +144,7 @@ struct jtag_ctrl
urj_vhdl_elem_t *vhdl_elem_last;
/* collected by BSDL parser */
char *idcode; /* IDCODE string */
+ char *port_grouping; /* PORT_GROUPING string */
char *usercode; /* USERCODE string */
int instr_len;
int bsr_len;
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