Hi, Here is* HOT Verification Engineer **requirement * for your consultants at *Dallas, TX.*
*Title:* *Verification Engineer* *Location: Dallas, TX.* *Duration: 12 Months * *Interview: Telephonic +Skype* *Requirements:* 7+ years of verification experience, with good experience in mixed signal chips PRIMARY ACTIVITIES: Verification of complex high speed digital logic with focus on SystemVerilog based Functional verification for a next generation Automotive chip. Primary responsibilities will include: verification planning, test case development, test case debug, coverage analysis, metric/status reporting and verification closure. TECHNICAL SKILLS:. Must have experience with SystemVerilog based verification for mixed-signal chips. Must know SystemVerilog. Must have excellent debug skills. Candidate should have experience in doing Functional Fault simulation. Any prior experience in Automotive chip functional/safety/Fault verification will be preferred. *Regards* *Vivek Nagare* *IDC Technologies Inc.* *Direct: 408-459-3307* *Skype: vivek.nagare1* *Email: [email protected] <[email protected]>* *Web: www.idctechnologies.com <http://www.idctechnologies.com/>* *US Office: IDC Technologies, Inc.,1851 McCarthy Boulevard, Suite 116, Milpitas, CA , USA, 95035* -- You received this message because you are subscribed to the Google Groups "US_IT.Groups" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at https://groups.google.com/group/us_itgroups. For more options, visit https://groups.google.com/d/optout.
