On Wednesday 30 November 2005 03:08, Hiten Pandya wrote: > Marko Zec wrote: > > Should we be really that pessimistic about potential MP > > performance, even with two NICs only? Typically packet flows are > > bi-directional, and if we could have one CPU/core taking care of > > one direction, then there should be at least some room for > > parallelism, especially once the parallelized routing tables see > > the light. Of course provided that each NIC is handled by a > > separate core, and that IPC doesn't become the actual bottleneck. > > On a similar note, it is important that we add the *hardware* support > for binding a set of CPUs to particular interrupt lines.
Yes that would be nice. Alternatively one could have separate polling threads on per-CPU/core basis for handling different interfaces. Maybe such a framework could even allow for migration of interfaces between polling threads, in order to dynamically adapt to different workloads / traffic patterns. With hardware interrupts such an idea would be very difficult if not completely impossible to implement. Marko > I believe > that the API support for CPU-affinitized interrupt threads is already > there so only the hard work is left of converting the APIC code from > physical to logical access mode. > > I am not sure how the AMD64 platform handles CPU affinity, by that I > mean if the same infrastructure put in place for i386 would work or > not with a few modifications here and there. The recent untangling > of the interrupt code should make it simpler for others to dig into > adding interrupt affinity support.