In message <zbdsjr8e5u+ju...@genode-labs.com> Stefan Kalkowski <stefan.kalkow...@genode-labs.com> wrote:
> > So that is the software architectural limitation right now. > Technically it should be no problem at all to route your interrupt to > CPU 1. One way to achieve this within an Genode-only system without > changing the IRQ service would be, to use the affinity of the caller > to set the CPU target. But if I remember correctly you want to route > the interrupt to a different core, which is managed by RISC OS. So in > that case you could either use a hack (just hardcode it for the > designated interrupts), or in the longer run the IRQ session gets > equipped with a way to express the affinity explicitely. The latter > solution however is nothing I would pledge to do overhasty. However, > we have to re-think the quite simple form of the IRQ session in the > midterm future anyway, because of other limitations, and we shall keep > your use-case in the back of our heads therefore. Replying from better client , thanks. > For an instant hack, you might have a look at file: > repos/base-hw/src/bootstrap/spec/arm/gicv3.cc > where the affinity routing of all interupts is initialized now. The > interesting register is `Distributor::Irouter` (line 53 in my > version). If I understand it right by reading real world example ( freertos/m4/imx8) it seems like MU should be set up using boot core. The manual doesn't mention this. I have tried to change in repos/base-hw/src/bootstrap/spec/arm/gicv3.cc In the loop that sets cpu .. how can I make it interrupting all cpus? I have tried this _irqdistr.write<Distributor::Irouter>(1U<<31, i); or by adding a bitfield struct i Irouter. Michael _______________________________________________ Genode users mailing list users@lists.genode.org https://lists.genode.org/listinfo/users