Hi, Thank you very much for the reply. It was failing for any arguments to xtimer_usleep (with 1000 for example). I thought i had already played with XTIMER_BACKOFF, XTIMER_ISR_BACKOFF and XTIMER_OVERHEAD but not enough apparently. Indeed, i have set all the three settings to 100 and my device succeeded to run several days without interruption. I will try to investigate deeper to know which minimal value could be used. Thank you again :)
Best regards, Aurélien 2017-08-30 23:12 GMT+02:00 Joakim Nohlgård <[email protected]>: > Hello Aurélien, > Is it failing for any arguments to xtimer_usleep, or is it only for > small values? > I don't have much experience with the STM32 platforms, so someone else > may have better insight into this, but this is the best idea that I > can think of: > When you reduce the core frequency you may have to adjust the xtimer > settings for XTIMER_BACKOFF, XTIMER_ISR_BACKOFF, and XTIMER_OVERHEAD. > I don't have any suggestions for any specific values, but you could > start by doubling the backoffs and see if the problem goes away. Using > a too large backoff constant wastes CPU cycles by actively spinning > for the timeout instead of letting the timer run in the background, > but these are very short time periods we are discussing here (tens of > microseconds). > > Hope this helps > > Best regards, > Joakim > > On Tue, Aug 29, 2017 at 3:55 PM, Aurélien Fillau > <[email protected]> wrote: > > Hello, > > > > I'm facing an issue with xtimer_usleep function. All is working fine for > a > > while but ramdomly, this function never returns, and my task stays > blocked. > > Actually, this is because the callback that is supposed to unlock the > mutex > > is never called. I have investigated and i saw that in xcore_timer.c:464, > > the second argument of the while is always false. > > I don't think this is the same issue as #7347. I tried to modified > > XTIMER_BACKOFF but without any success. > > Here is my clock configuration : > > > > `#define CLOCK_HSI (16000000U) /* internal > > oscillator */ > > #define CLOCK_CORECLOCK (16000000U) /* desired core clock > > frequency */ > > > > /* configuration of PLL prescaler and multiply values */ > > /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */ > > #define CLOCK_PLL_DIV RCC_CFGR_PLLDIV4 > > #define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4 > > /* configuration of peripheral bus clock prescalers */ > > #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV8 /* AHB clock -> > 2MHz > > */ > > #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> > 2MHz > > */ > > #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> > 2MHz > > */ > > /* configuration of flash access cycles */ > > #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY > > > > /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! > */ > > #define CLOCK_AHB (CLOCK_CORECLOCK / 8) > > #define CLOCK_APB2 (CLOCK_CORECLOCK / 8) > > #define CLOCK_APB1 (CLOCK_CORECLOCK / 8) > > > > #define ENABLE_LSI (1) > > > > /** > > * @name Timer configuration > > * @{ > > */ > > static const timer_conf_t timer_config[] = { > > { > > .dev = TIM2, > > .max = 0x0000ffff, > > .rcc_mask = RCC_APB1ENR_TIM2EN, > > .bus = APB1, > > .irqn = TIM2_IRQn > > } > > }; > > > > #define TIMER_0_ISR isr_tim2 > > #define TIMER_NUMOF (sizeof(timer_config) / > > sizeof(timer_config[0]))` > > > > I have reduced all clocks to save power. I'm working on a stm32l073. > > > > If you have any ideas about this issue, feel free to share your thoughts > :) > > > > Thank you in advance, > > > > Aurélien > > > > > > _______________________________________________ > > users mailing list > > [email protected] > > https://lists.riot-os.org/mailman/listinfo/users > > > _______________________________________________ > users mailing list > [email protected] > https://lists.riot-os.org/mailman/listinfo/users >
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