This is Gaurav, working with SysMind. We have the below contract job
opportunity with one of our direct clients and would like to check if you
have any resources available. Please send across the resume of your
consultants along with the contact information at the earliest to
[email protected] or call me at 609-897-9670 X2154
Role: Verification Engineer
Location: Allentown, PA
Duration: C2H
Interview type: Telephonic/Skype
Description:
1. Role: Pre-Silicon functional verification Senior Engineer:
2. Qualification: MS-EE / B-Tech – EE/ECE
3. Experience Level: 4+ Years
4. Skill set and experience
a. At least 3+ years’ experience in pre-silicon verification
b. Expertise in Building scalable HVL based verification environment
from Scratch using System Verilog OVM/UVM
c. Good experience in System Verilog – OVM/UVM based verification
environment development
d. Sound understanding of Random and constrained random-verification
concepts
e. Experience with assertion based verification would be a plus
f. Understanding PCI-E, USB, SATA, DDR3 type protocols would be a
plus
5. Role included:
a. Driving the verification environment architecture
b. Creating test scenarios(System Verilog OVM)
c. Work with RTL teams to debug verification failures
d. Review and ensure that expected Code and functional coverage
metrics are achieved
Gaurav Nagar
Phone: 609-897-9670 x2154
Email: [email protected]
Fax: 609-228-5522
Address: 38 Washington Road, Princeton Jn, NJ 08550
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