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Today's Topics:
1. USRP N210+DBSRX2 internal noise (Marc Epard)
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Message: 1
Date: Thu, 17 Mar 2011 07:51:33 -0500
From: Marc Epard <[email protected]>
To: [email protected]
Subject: [USRP-users] USRP N210+DBSRX2 internal noise
Message-ID: <[email protected]>
Content-Type: text/plain; charset="us-ascii"
We've customized an FPGA image for the N210 that lets us grab batches of 256K
complex samples (one SRAM full) at 100 Msps with no decimation, scaling, or
downconversion. Among other things, we've used it to look at internal noise
with the DBSRX2. The plot below shows power at +10MHz in the baseband at each
center frequency. You'll also find two color plots at
https://public.me.com/mepard that show the entire 100 MHz baseband spectrum
against each center frequency, one of the full 800-2400 MHz range and one
zoomed in on 1400 - 1600 MHz. The samples were collected with rx gain set to 52
dB and no signal source connected to the DBSRX2.
It looks like there are harmonics of a 100 MHz clock (the sample clock or the
reference from the motherboard, perhaps), a 25 MHz clock (maybe the output of
the divider), plus some other components. In the false color plots you can see
components that decrease in baseband frequency as the center frequency
increases (what I'd expect from scanning across a stationary frequency), but
also components that increase with the center frequency and at various rates.
First, does this look as expected? Second, does anyone have suggestions for
reducing any of this?
TIA. -Marc
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