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Today's Topics:
1. Re: timing constraints and resource utilization for usrp2
fpga code (Nick Foster)
2. Re: timing constraints and resource utilization for usrp2
fpga code (Arun Pillai)
3. Problem with DBSRX2 USRP1 Simulink (Paola Madonna)
----------------------------------------------------------------------
Message: 1
Date: Tue, 22 Mar 2011 22:54:22 -0700
From: Nick Foster <[email protected]>
To: Arun Pillai <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] timing constraints and resource utilization
for usrp2 fpga code
Message-ID: <1300859662.12468.27.camel@crapshoot>
Content-Type: text/plain; charset="UTF-8"
On Wed, 2011-03-23 at 01:44 -0400, Arun Pillai wrote:
> Hi,
>
> I downloaded and compiled the UHD fpga code for USRP2 using Xilinx 12.4.
> However, its resource utilization seems way higher than the original
> non-UHD fpga code that worked with Xilinx 10.3.
The UHD image is doing a whole lot more than the non-UHD image did. You
get UDP, real flow control, transmit buffering using the SRAM,
synchronization, MIMO cable support, etc.
<snip>
> Also, the UHD code is failing to meet timing. Is this going to lead to
> flakiness or problems when running the code? Are there options I can set
> to get the code to meet timing, at the cost of greater compile time?
Is it close, or is it totally missing timing? ISE's somewhat
nondeterministic behavior means that different versions of ISE can
produce very different results. We use 12.1, and the build meets timing.
--n
>
> Thanks,
> Arun
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
------------------------------
Message: 2
Date: Wed, 23 Mar 2011 02:55:45 -0400
From: Arun Pillai <[email protected]>
To: Nick Foster <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] timing constraints and resource utilization
for usrp2 fpga code
Message-ID: <[email protected]>
Content-Type: text/plain; charset="utf-8"; Format="flowed"
>> Also, the UHD code is failing to meet timing. Is this going to lead to
>> flakiness or problems when running the code? Are there options I can set
>> to get the code to meet timing, at the cost of greater compile time?
>
> Is it close, or is it totally missing timing? ISE's somewhat
> nondeterministic behavior means that different versions of ISE can
> produce very different results. We use 12.1, and the build meets timing.
It seems to be missing by a lot. PAR says after the final phase that:
Phase 9 : 0 unrouted; (Setup:20497, Hold:0, Component Switching
Limit:0) REAL time: 4 mins 1 secs
I have also attached the PAR log, which has the full information.
arun
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Message: 3
Date: Wed, 23 Mar 2011 11:10:34 +0100
From: "Paola Madonna" <[email protected]>
To: <[email protected]>
Subject: [USRP-users] Problem with DBSRX2 USRP1 Simulink
Message-ID: <[email protected]>
Content-Type: text/plain; charset="us-ascii"
Hello,
I have bought a USRP1 and a DBSRX2 dautherboard. I have installed the
drivers for Simulink as indicated in your web site but the dautherboard
results unknown using the block user_helper in the USRP library of Simulink
and so it doesn't acquire the gps signal from antenna. I have read on your
website that the DBSRX2 needs UHD driver so the driver installed recognizes
only the motherboard USRP1 and not the dautherboard. Now I am installing UHD
driver under windows but I am asking how to use the uhd driver with Simulink
and if I can use the USRP library of Simulink as indicated on your website.
Please help me as soon as possible.
Greetings,
--------------------------------
Ing. Paola Madonna
TRS S.p.A.
Via Giulio Cesare 105
c/o Selex-SI, Stab. Fusaro
80070 Bacoli (NA)
Italy
Ph.:+39 (0)81 52 72 837
Fax: +39 (0)81 52 72 828
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