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Today's Topics:
1. USRP Calibration Routine (Dan CaJacob)
2. Re: How do I reset the DSP on the E110? (Thomas Tsou)
3. Re: USRP1 UHD and GPIO + a quick USRP B100 question
(Mark Cottrell)
4. Re: USRP Calibration Routine (Jason Abele)
5. Error on the page UHD_Linux (Farhad Abdolian)
6. Re: USRP1 UHD and GPIO + a quick USRP B100 question (Josh Blum)
7. FPGA and FW update of N210 (Farhad Abdolian)
8. Re: FPGA and FW update of N210 (Jonathan Fox)
9. Re: FPGA and FW update of N210 ([email protected])
10. Re: FPGA and FW update of N210 ([email protected])
11. Re: FPGA and FW update of N210 (Farhad Abdolian)
12. Re: FPGA and FW update of N210 (Orkhan Badirkhanli)
----------------------------------------------------------------------
Message: 1
Date: Wed, 04 Apr 2012 12:04:53 -0400
From: Dan CaJacob <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] USRP Calibration Routine
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
Hi Josh,
In some of the documentation for the three calibration utilities, you
have indicated that the RF ports on the daughter-card being calibrated
should be disconnected. I have always done that, but I was wondering if
50 Ohm terminations on the connectors would be of any benefit? Thanks.
--
Very Respectfully,
Dan CaJacob
------------------------------
Message: 2
Date: Wed, 4 Apr 2012 14:19:51 -0400
From: Thomas Tsou <[email protected]>
To: "Jiang, Leaf - 1006 - MITLL" <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] How do I reset the DSP on the E110?
Message-ID:
<CAF5FEsBbSRuwxjjQL=jr8w6k6fc1ee2dt2cfffpy82n0f9a...@mail.gmail.com>
Content-Type: text/plain; charset=ISO-8859-1
On Wed, Apr 4, 2012 at 9:59 AM, Jiang, Leaf - 1006 - MITLL
<[email protected]> wrote:
> Hi Philip and Thomas,
>
> I just tried the new image from?http://files.ettus.com/e1xx_images/current/
> and the lpm module loads without error. ?The only problem now is that lpm
> doesn't seem
> to be resetting the dsp. ?The output below shows that the first program
> (loopgpp) runs fine, but the second program (messagegpp) freezes. ?Even
> after running lpmON/OFF, the second program still freezes.? Any ideas why?
Strange. It worked for me on the new image and my old combination.
@usrp-e1xx:/usr/share/ti/ti-dsplink-examples# ./messagegpp message.out 1000
========== Sample Application : MESSAGE ==========
Entered MESSAGE_Create ()
Leaving MESSAGE_Create ()
Entered MESSAGE_Execute ()
Transferring 10000 iterations took 2 seconds 689483 microseconds.
RoundTrip Time for 1 message is 268 microseconds.
Leaving MESSAGE_Execute ()
Entered MESSAGE_Delete ()
Leaving MESSAGE_Delete ()
root@usrp-e1xx:/usr/share/ti/ti-dsplink-examples# ../ti-lpm-utils/lpmOFF.xv5T
==== LPM OFF Test ====
app: LPM_open
app: LPM_set(LPM_CTRL_REFCOUNTOVR)
app: LPM_off
app: LPM_close
==== LPM OFF test completed ====
root@usrp-e1xx:/usr/share/ti/ti-dsplink-examples# ../ti-lpm-utils/lpmON.xv5T
==== LPM ON Test ====
app: LPM_open
app: LPM_set(LPM_CTRL_REFCOUNTOVR)
app: LPM_on
root@usrp-e1xx:/usr/share/ti/ti-dsplink-examples# ./loopgpp loop.out 1024 2000 0
=============== Sample Application : LOOP ==========loopgpp loop.out
1024 2000 0
==== Executing sample for DSP processor Id 0 ====
Entered LOOP_Create ()
Leaving LOOP_Create ()
Entered LOOP_Execute ()
Transferred 1000 buffers
Transferred 2000 buffers
Leaving LOOP_Execute ()
Entered LOOP_Delete ()
Leaving LOOP_Delete ()
====================================================
Thomas
------------------------------
Message: 3
Date: Thu, 5 Apr 2012 09:38:23 +1200
From: Mark Cottrell <[email protected]>
To: [email protected]
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] USRP1 UHD and GPIO + a quick USRP B100
question
Message-ID:
<cajv9sbgy3ljrf9ymknlegn0xl+eccu4k9r0ipq5v5js+jbi...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi Josh,
I finally got my hands on a B100 and have been playing around with the
modification you suggested. Just putting pps_in in there resulted
"ERROR:Xst:871 - "../u1plus_core.v" line 159: Invalid use of input signal
<pps_in> as target.", so not being very familiar verilog I have tried "wire
pps_out = pps_in;" and "assign pps_out = pps_in;", then passing it through
with the samples (i.e. http://pastebin.com/t20QEc36), but haven't had much
luck. I have uploaded some screen captures that indicate that I have
succeeded in replacing the least significant bit with a zero (
http://imgur.com/a/EW4S2), but the 1PPS is nowhere to be seen.
Do I need to make any modifications to the ddc_chain module to get this to
work? I am a bit out of my depth here, so any further suggestions would be
appreciated.
Thanks,
Mark
On Thu, Mar 8, 2012 at 10:08 AM, Josh Blum <[email protected]> wrote:
>
> > My question about the USRP B100 again relates 1PPS stuff. If I have a
> 1PPS
> > connected to a B100, is it possible to embed the 1PPS signal in the
> > received stream in a similar fashion to the above gr-usrp/gr-gpio
> approach?
> >v
>
> Ahh, the use a PPS input as a trigger paradigm.
>
> If you want the trigger signal inline with the stream, this diff should
> work for you: http://pastebin.com/8wGa8SVc
>
> Without modifying any FPGA code, this is the simplest.
> You can poll usrp->get_time_last_pps(), now you know the time the PPS
> "triggered". And the receive stream has timestamps, so you can know
> precisely know which sample had the trigger event.
>
> Also see this for a more detailed set of options:
> http://www.ruby-forum.com/topic/3644205#1048591
>
> -Josh
>
=======================================================================
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------------------------------
Message: 4
Date: Wed, 4 Apr 2012 14:52:14 -0700
From: Jason Abele <[email protected]>
To: Dan CaJacob <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] USRP Calibration Routine
Message-ID: <20120404215213.GI31175@nettles>
Content-Type: text/plain; charset=us-ascii
On Wed, Apr 04, 2012 at 12:04:53PM -0400, Dan CaJacob wrote:
> Hi Josh,
>
> In some of the documentation for the three calibration utilities, you
> have indicated that the RF ports on the daughter-card being
> calibrated should be disconnected. I have always done that, but I
> was wondering if 50 Ohm terminations on the connectors would be of
> any benefit? Thanks.
It won't hurt anything, but I doubt it will change much. The most
likely change would be in RX DC/LO which is not statically calibrated,
instead, it is handled by an average and subtract operation in the FPGA.
During cal, the TX is switched away from the TX antenna into the
"closed" switch port, where it leaks into the RX which is listening to
the TX/RX antenna.
So termination on RX2 should have no effect as that port is already
unused in calibration.
However, the calibration code is open-source and there is no real reason
you can't experiment with other configurations or use the concepts
within it to fit the calibration routines to your application/system
design. It is important to note that transmitting close to full-power
directly into the receiver is likely to result in hardware damage, so
be careful of your settings and power-levels if you modify the
calibration routines.
Jason
------------------------------
Message: 5
Date: Wed, 4 Apr 2012 15:12:49 -0700 (PDT)
From: Farhad Abdolian <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] Error on the page UHD_Linux
Message-ID:
<[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
Hi Guys,
I tried to install UHD on a new computer and found a problem on this page:
http://code.ettus.com/redmine/ettus/projects/uhd/wiki/UHD_Linux
sudo bash -c 'echo "deb
http://files.ettus.com/binaries/stable/repo/uhd/ubuntu/`lsb_release -cs`
`lsb_release -cs` main" > /etc/apt/sources.list.d/ettus.list'
sudo apt-get update
sudo apt-get install uhd
The directory on ettus has change to :
??? http://files.ettus.com/binaries/uhd_stable/repo/uhd/ubuntu/
Best regards,
Farhad
>________________________________
> From: Jason Abele <[email protected]>
>To: Dan CaJacob <[email protected]>
>Cc: "[email protected]" <[email protected]>
>Sent: Wednesday, April 4, 2012 11:52 PM
>Subject: Re: [USRP-users] USRP Calibration Routine
>
>On Wed, Apr 04, 2012 at 12:04:53PM -0400, Dan CaJacob wrote:
>> Hi Josh,
>>
>> In some of the documentation for the three calibration utilities, you
>> have indicated that the RF ports on the daughter-card being
>> calibrated should be disconnected.? I have always done that, but I
>> was wondering if 50 Ohm terminations on the connectors would be of
>> any benefit?? Thanks.
>
>It won't hurt anything, but I doubt it will change much.? The most
>likely change would be in RX DC/LO which is not statically calibrated,
>instead, it is handled by an average and subtract operation in the FPGA.
>
>During cal, the TX is switched away from the TX antenna into the
>"closed" switch port, where it leaks into the RX which is listening to
>the TX/RX antenna.
>
>So termination on RX2 should have no effect as that port is already
>unused in calibration.
>
>However, the calibration code is open-source and there is no real reason
>you can't experiment with other configurations or use the concepts
>within it to fit the calibration routines to your application/system
>design.? It is important to note that transmitting close to full-power
>directly into the receiver is likely to result in hardware damage, so
>be careful of your settings and power-levels if you modify the
>calibration routines.
>
>Jason
>
>_______________________________________________
>USRP-users mailing list
>[email protected]
>http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
>
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------------------------------
Message: 6
Date: Wed, 04 Apr 2012 15:26:49 -0700
From: Josh Blum <[email protected]>
To: Mark Cottrell <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] USRP1 UHD and GPIO + a quick USRP B100
question
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1
On 04/04/2012 02:38 PM, Mark Cottrell wrote:
> Hi Josh,
>
> I finally got my hands on a B100 and have been playing around with the
> modification you suggested. Just putting pps_in in there resulted
> "ERROR:Xst:871 - "../u1plus_core.v" line 159: Invalid use of input signal
> <pps_in> as target.", so not being very familiar verilog I have tried "wire
> pps_out = pps_in;" and "assign pps_out = pps_in;", then passing it through
> with the samples (i.e. http://pastebin.com/t20QEc36), but haven't had much
> luck. I have uploaded some screen captures that indicate that I have
> succeeded in replacing the least significant bit with a zero (
> http://imgur.com/a/EW4S2), but the 1PPS is nowhere to be seen.
>
> Do I need to make any modifications to the ddc_chain module to get this to
> work? I am a bit out of my depth here, so any further suggestions would be
> appreciated.
>
I must have not been thinking, the pps in should go into the framer
input. Try this diff: http://pastebin.com/7TX3Beiy
That should be all the mods you need to get the LSB to be the PPS signal.
-Josh
> Thanks,
> Mark
>
> On Thu, Mar 8, 2012 at 10:08 AM, Josh Blum <[email protected]> wrote:
>
>>
>>> My question about the USRP B100 again relates 1PPS stuff. If I have a
>> 1PPS
>>> connected to a B100, is it possible to embed the 1PPS signal in the
>>> received stream in a similar fashion to the above gr-usrp/gr-gpio
>> approach?
>>> v
>>
>> Ahh, the use a PPS input as a trigger paradigm.
>>
>> If you want the trigger signal inline with the stream, this diff should
>> work for you: http://pastebin.com/8wGa8SVc
>>
>> Without modifying any FPGA code, this is the simplest.
>> You can poll usrp->get_time_last_pps(), now you know the time the PPS
>> "triggered". And the receive stream has timestamps, so you can know
>> precisely know which sample had the trigger event.
>>
>> Also see this for a more detailed set of options:
>> http://www.ruby-forum.com/topic/3644205#1048591
>>
>> -Josh
>>
>
> =======================================================================
> This email, including any attachments, is only for the intended
> addressee. It is subject to copyright, is confidential and may be
> the subject of legal or other privilege, none of which is waived or
> lost by reason of this transmission.
> If the receiver is not the intended addressee, please accept our
> apologies, notify us by return, delete all copies and perform no
> other act on the email.
> Unfortunately, we cannot warrant that the email has not been
> altered or corrupted during transmission.
> =======================================================================
>
------------------------------
Message: 7
Date: Thu, 5 Apr 2012 06:26:59 -0700 (PDT)
From: Farhad Abdolian <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] FPGA and FW update of N210
Message-ID:
<[email protected]>
Content-Type: text/plain; charset="us-ascii"
Hi,
How
do I know what revision my USRP N210 is? I am trying to update the FPGA
image on the 2 USRPs I have and don't know which FPGA code to use.
The problem I have is that I can not detect the USRPs using uhd_find_devices.
I can ping the USRP and I can upgrade the FW but I can not 'detect' it and use
it.
Really appreciate your help,
BR,
Farhad
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Message: 8
Date: Thu, 5 Apr 2012 09:42:27 -0400
From: Jonathan Fox <[email protected]>
To: Farhad Abdolian <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] FPGA and FW update of N210
Message-ID:
<CAPZrquas7gm2sy=RxWxBK_LsnGBeC-E3iab6ZNFWE=t5nzb...@mail.gmail.com>
Content-Type: text/plain; charset=ISO-8859-1
Farhad,
Please try "uhd_usrp_probe".
-Jon
On 4/5/12, Farhad Abdolian <[email protected]> wrote:
> Hi,
> How
> do I know what revision my USRP N210 is? I am trying to update the FPGA
> image on the 2 USRPs I have and don't know which FPGA code to use.
>
> The problem I have is that I can not detect the USRPs using
> uhd_find_devices.
>
> I can ping the USRP and I can upgrade the FW but I can not 'detect' it and
> use it.
>
> Really appreciate your help,
>
> BR,
> Farhad
------------------------------
Message: 9
Date: Thu, 05 Apr 2012 10:07:51 -0400
From: [email protected]
To: <[email protected]>
Subject: Re: [USRP-users] FPGA and FW update of N210
Message-ID: <[email protected]>
Content-Type: text/plain; charset="utf-8"
On Fedora, certain types of broadcast packets are blocked for
non-root users, and that's how "find devices" works.
Try:
uhd_usrp_probe --args "addr=192.168.10.2"
On Thu, 5 Apr 2012
09:42:27 -0400, Jonathan Fox wrote:
> Farhad,
>
> Please try
"uhd_usrp_probe".
>
> -Jon
>
> On 4/5/12, Farhad Abdolian wrote:
>>
Hi, How do I know what revision my USRP N210 is? I am trying to update
the FPGA image on the 2 USRPs I have and don't know which FPGA code to
use. The problem I have is that I can not detect the USRPs using
uhd_find_devices. I can ping the USRP and I can upgrade the FW but I can
not 'detect' it and use it. Really appreciate your help, BR, Farhad
>
_______________________________________________ USRP-users mailing list
[email protected] [2]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com [3]
Links:
------
[1] mailto:[email protected]
[2]
mailto:[email protected]
[3]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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------------------------------
Message: 10
Date: Thu, 05 Apr 2012 10:10:06 -0400
From: [email protected]
To: <[email protected]>
Subject: Re: [USRP-users] FPGA and FW update of N210
Message-ID: <[email protected]>
Content-Type: text/plain; charset="utf-8"
There's a sticker on the back of the device that tells you the
hardware Rev.
Both Rev2 and Rev3 devices share the same codebase, so
the FPGA/FW images are identical. The Rev 4 needs its own codebase.
On
Thu, 5 Apr 2012 06:26:59 -0700 (PDT), Farhad Abdolian wrote:
> Hi,
>
How do I know what revision my USRP N210 is? I am trying to update the
FPGA image on the 2 USRPs I have and don't know which FPGA code to
use.
>
> The problem I have is that I can not detect the USRPs using
uhd_find_devices.
>
> I can ping the USRP and I can upgrade the FW but
I can not 'detect' it and use it.
>
> Really appreciate your help,
>
>
BR,
> Farhad
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Message: 11
Date: Thu, 5 Apr 2012 07:20:29 -0700 (PDT)
From: Farhad Abdolian <[email protected]>
To: "[email protected]" <[email protected]>,
"[email protected]" <[email protected]>
Subject: Re: [USRP-users] FPGA and FW update of N210
Message-ID:
<[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
Excellent, I will check it out and see if I can communicate with my USRPs when
I get home.
>________________________________
> From: "[email protected]" <[email protected]>
>To: [email protected]
>Sent: Thursday, April 5, 2012 4:10 PM
>Subject: Re: [USRP-users] FPGA and FW update of N210
>
>
>There's a sticker on the back of the device that tells you the hardware Rev.
>Both Rev2 and Rev3 devices share the same codebase, so the FPGA/FW images are
>identical.? The Rev 4 needs its own codebase.
>?
>On Thu, 5 Apr 2012 06:26:59 -0700 (PDT), Farhad Abdolian wrote:
>Hi,
>>How do I know what revision my USRP N210 is? I am trying to update the FPGA
>>image on the 2 USRPs I have and don't know which FPGA code to use.
>>
>>The problem I have is that I can not detect the USRPs using uhd_find_devices.
>>
>>I can ping the USRP and I can upgrade the FW but I can not 'detect' it and
>>use it.
>>
>>Really appreciate your help,
>>
>>BR,
>>Farhad
>?
>_______________________________________________
>USRP-users mailing list
>[email protected]
>http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
>
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------------------------------
Message: 12
Date: Thu, 5 Apr 2012 17:28:52 +0300
From: Orkhan Badirkhanli <[email protected]>
To: Farhad Abdolian <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] FPGA and FW update of N210
Message-ID:
<cadl6qmeblwkhsyr7tb6tzbef4ry7wxve7kz08wajeu1wkhs...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
In my case with n210 when I tried to burn wrong image, the error message
would notify me of the right revision to use
On Thu, Apr 5, 2012 at 5:20 PM, Farhad Abdolian <[email protected]>wrote:
> Excellent, I will check it out and see if I can communicate with my USRPs
> when I get home.
>
> ------------------------------
> *From:* "[email protected]" <[email protected]>
> *To:* [email protected]
> *Sent:* Thursday, April 5, 2012 4:10 PM
> *Subject:* Re: [USRP-users] FPGA and FW update of N210
>
> There's a sticker on the back of the device that tells you the hardware
> Rev.
> Both Rev2 and Rev3 devices share the same codebase, so the FPGA/FW images
> are identical. The Rev 4 needs its own codebase.
>
> On Thu, 5 Apr 2012 06:26:59 -0700 (PDT), Farhad Abdolian wrote:
>
> Hi,
> How do I know what revision my USRP N210 is? I am trying to update the
> FPGA image on the 2 USRPs I have and don't know which FPGA code to use.
>
> The problem I have is that I can not detect the USRPs using
> uhd_find_devices.
>
> I can ping the USRP and I can upgrade the FW but I can not 'detect' it and
> use it.
>
> Really appreciate your help,
>
> BR,
> Farhad
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
--
Orkhan
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End of USRP-users Digest, Vol 20, Issue 5
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