Send USRP-users mailing list submissions to
[email protected]
To subscribe or unsubscribe via the World Wide Web, visit
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
or, via email, send a message with subject or body 'help' to
[email protected]
You can reach the person managing the list at
[email protected]
When replying, please edit your Subject line so it is more specific
than "Re: Contents of USRP-users digest..."
Today's Topics:
1. Analogue Bandwidth Setting (John Shields)
2. questions about usrp-e-loopback (Ahmed Alsawi)
3. Re: Analogue Bandwidth Setting (Marcus D. Leech)
4. Re: Analogue Bandwidth Setting (John Shields)
5. Re: How to use XILINX Platform Cable for FPGA testing on
E110.? Where is the JTAG port on E110? (xi yang)
----------------------------------------------------------------------
Message: 1
Date: Sun, 15 Apr 2012 07:14:12 +1200
From: "John Shields" <[email protected]>
To: "usrp-users" <[email protected]>
Subject: [USRP-users] Analogue Bandwidth Setting
Message-ID: <D866BB84C4AA47F18906D43CF7A567A6@FIFE>
Content-Type: text/plain; charset="iso-8859-1"
( Ubuntu 10.04, N210 rev 4 various dbs, UHD_003.004.000-1-gea19de0b)
Some of the rx and tx/rx daughterboards appear to have analogue filters and, in
my dumb Scottish way, I thought that setting the 'bandwidth' option in the
USRP_source block in GRC would have the desired effect but I don't see it on
the FFT; the python call is generated correctly.
Specifically for the DBSRX2, with freq range ( 800 - 2350 ) - the product page
says " programmable 1-60 MHz channel filter that allows users to serve a wide
variety of applications while providing the appropriate level of selectivity in
the analog path. ".
When I grep-ed the UHD git, I see that set_bandwidth gets passed to
set_rx_bandwidth for RX but the only target I can see for that is with
db_xcvr2450.cpp in the db directory.
Is there a different mechanism for setting analogue filters on other dbs which
support such?
If I have db with this capability, what is the 'default' setting? persumably
driven by sample_rate ( 4 Mhz in my case ).?
Kind Regards,
John
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/attachments/20120415/1efe3d68/attachment-0001.html>
------------------------------
Message: 2
Date: Sat, 14 Apr 2012 21:26:33 +0200
From: Ahmed Alsawi <[email protected]>
To: [email protected]
Subject: [USRP-users] questions about usrp-e-loopback
Message-ID:
<ca+9pi22lgsyp5rebkbbx0nbqg8dxeknwrc3c+y3ycsfsrq-...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Dear all,
I am working on E100 ,, when i run
/usr/share/uhd/example/usrp-utils/usrp-e-loopback
root@usrp-e1xx:/usr/share/uhd/examples# ./usrp-e-loopback
setup memory mapped ring buffer... done
start write thread...
start read thread...
..........
seq_errors 0
checksum_errors 0
sent_words32 56877948
recvd_words32 560912
approx send rate 5.68779Msps
approx recv rate 0.0560912Msps
how come the recvd is less than sent and both errors are zero ?
I run it several times and it always 2 different numbers.
did anyone try these binaries and have the same results ?
Thanks
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/attachments/20120414/01aa0e21/attachment-0001.html>
------------------------------
Message: 3
Date: Sat, 14 Apr 2012 15:34:24 -0400
From: "Marcus D. Leech" <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] Analogue Bandwidth Setting
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"; Format="flowed"
On 04/14/2012 03:14 PM, John Shields wrote:
> ( Ubuntu 10.04, N210 rev 4 various dbs, UHD_003.004.000-1-gea19de0b)
> Some of the rx and tx/rx daughterboards appear to have analogue
> filters and, in my dumb Scottish way, I thought that setting the
> 'bandwidth' option in the USRP_source block in GRC would have the
> desired effect but I don't see it on the FFT; the python call is
> generated correctly.
> Specifically for the DBSRX2, with freq range ( 800 - 2350 ) - the
> product page says " programmable 1-60 MHz channel filter that allows
> users to serve a wide variety of applications while providing the
> appropriate level of selectivity in the analog path. ".
> When I grep-ed the UHD git, I see that set_bandwidth gets passed to
> set_rx_bandwidth for RX but the only target I can see for that is with
> db_xcvr2450.cpp in the db directory.
> Is there a different mechanism for setting analogue filters on other
> dbs which support such?
> If I have db with this capability, what is the 'default' setting?
> persumably driven by sample_rate ( 4 Mhz in my case ).?
> Kind Regards,
> John
For relatively-recent UHD instances, the daughtercard bandwidth is set
appropriate for the Nyquist limit of whatever motherboard it's plugged into.
So for USRP1/B100/E100/E110 it'll get set to somewhere around 50MHz
and for USRP2/N2XXX, somewhere around 80MHz. What gets
delivered to you, of course, is the decimated chunk of that
bandwidth, which has had out-of-band goo attenuated by 80dB or more by
the digital filtering in the FPGA.
There's ordinarily not much reason to set the analog bandwidth, since
the anti-aliasing filters work reasonably well to present a bandwidth
that is "Nyquist well-behaved" to the fixed-rate samplers.
There *is* a set_bandwidth method in db_dbsrx2.cpp in UHD, and as far as
I know, it works.
--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/attachments/20120414/e389444c/attachment-0001.html>
------------------------------
Message: 4
Date: Sun, 15 Apr 2012 10:16:09 +1200
From: "John Shields" <[email protected]>
To: "Marcus D. Leech" <[email protected]>,
<[email protected]>
Subject: Re: [USRP-users] Analogue Bandwidth Setting
Message-ID: <BECAF9DB98EF467AAAAE8A9465B60DCA@FIFE>
Content-Type: text/plain; charset="iso-8859-1"
You are indeed correct, Marcus. Not sure how I missed that - window issue :)
With SBX and DBSRX2, I was seeing a 'rounded' FFT so was trying to see if
Analogue filter was somehow implicated and this led me down the path. I know
that from an e-mail exchange with yourself and Josh some time ago, there was
mention that the roll-off will occur within the Nyquist limit and that you
needed to sample reciprocal of .8 to get flat reponse or something like that?
which implied to me that if you wanted a 'flat' 1 MHz b/w, you should sample at
1.25 msps (x2 depending on complex)
Thanks,
Kind Regards,
John
----- Original Message -----
From: Marcus D. Leech
To: [email protected]
Sent: Sunday, April 15, 2012 7:34 AM
Subject: Re: [USRP-users] Analogue Bandwidth Setting
On 04/14/2012 03:14 PM, John Shields wrote:
( Ubuntu 10.04, N210 rev 4 various dbs, UHD_003.004.000-1-gea19de0b)
Some of the rx and tx/rx daughterboards appear to have analogue filters
and, in my dumb Scottish way, I thought that setting the 'bandwidth' option in
the USRP_source block in GRC would have the desired effect but I don't see it
on the FFT; the python call is generated correctly.
Specifically for the DBSRX2, with freq range ( 800 - 2350 ) - the product
page says " programmable 1-60 MHz channel filter that allows users to serve a
wide variety of applications while providing the appropriate level of
selectivity in the analog path. ".
When I grep-ed the UHD git, I see that set_bandwidth gets passed to
set_rx_bandwidth for RX but the only target I can see for that is with
db_xcvr2450.cpp in the db directory.
Is there a different mechanism for setting analogue filters on other dbs
which support such?
If I have db with this capability, what is the 'default' setting?
persumably driven by sample_rate ( 4 Mhz in my case ).?
Kind Regards,
John
For relatively-recent UHD instances, the daughtercard bandwidth is set
appropriate for the Nyquist limit of whatever motherboard it's plugged into.
So for USRP1/B100/E100/E110 it'll get set to somewhere around 50MHz and
for USRP2/N2XXX, somewhere around 80MHz. What gets
delivered to you, of course, is the decimated chunk of that bandwidth,
which has had out-of-band goo attenuated by 80dB or more by
the digital filtering in the FPGA.
There's ordinarily not much reason to set the analog bandwidth, since the
anti-aliasing filters work reasonably well to present a bandwidth
that is "Nyquist well-behaved" to the fixed-rate samplers.
There *is* a set_bandwidth method in db_dbsrx2.cpp in UHD, and as far as I
know, it works.
--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
------------------------------------------------------------------------------
_______________________________________________
USRP-users mailing list
[email protected]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/attachments/20120415/5e7aa41c/attachment-0001.html>
------------------------------
Message: 5
Date: Sat, 14 Apr 2012 19:59:19 -0400
From: xi yang <[email protected]>
To: Ahmed Alsawi <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] How to use XILINX Platform Cable for FPGA
testing on E110.? Where is the JTAG port on E110?
Message-ID:
<cal6exzpki7f0k7t9whfxitfs8zoxng7ugyoek-mz0jqx1xk...@mail.gmail.com>
Content-Type: text/plain; charset="gb2312"
Hi Ahmed,
Before I try my FPGA codes on E110, I had tested it on E100. I use
chipscope to capture signals. My steps are as follow, hope they can help
you.
For your question 1, you need to do these operations on Linux system. You
make new images on your Linux system (e.g., "usrp_e100_fpga.bin" for
E100). The E100 loads images from /usr/share/uhd/images by default. To
make your image effective, you copy your own image to E100 by scp
usrp_e100_fpga.bin root@(the ip address of your
usrp):/usr/share/uhd/images. Now you changed the image to the one you just
compiled. So before you replace the original image, you should backup it.
For your question 2: 1) add new source, and select ?ChipScope Definition
and Connection? to a .cdc file. When you create your own image
"usrp_e100_fpga.bin" through the command "make images", you need to
inlcude the .cdc file in your makefile file.
2). Also you can see the CDC file under the top moudle. Click the CDC file,
open "ChipScope Core Inserter".
3). Configer all of the parameters in "chipscope core inseter", include
.device options, ILA parameters. You cannot configer the ICON paeameters,
because it shows "No ICON parameters exist for the selected device family".
4) after connected all of the trigger ports, data ports and clock port,
click on "return to project navigator". Then, save project and run
implementation. In this step, you must choose a right clock as the clock
port(For e100, I choose clk_fpga as the clock port), and choose the signals
that you want to analysis as data ports.
5)click on properties of "Generate Programming File", enable JTAG clock as
StartUpClk and enable the data read back property too.
6) Then you can generate a bit file.
7) After that, click "analyze using chipscope analyzer"at the end of the
process tree.
8) A new chipscope analyzer window was opend. Click on the chain initialize
button symbolized by four black squares in the top left.
9) Then, click [Device]/[Configure], select the right device, click the
"select new file" buttom to choose your bit file. Then Fpga can download
the bit file.
10) Also add CDC file, then click "Trigger Setup". In "match" window
choose a right logic form to be the trigger condition.
11) Choose depth of capture and add all of signal you choosed in to
waveform window.
12) Then, i click "run" to capture the sample.
Good luck!
Yooxi
2012/4/14 Ahmed Alsawi <[email protected]>
> Dear sir,
> I hope you don't mind contacting off list.
> i have E100 and ,,I have 2 question
> - how can i reload fpga image on demand?
> - you mentioned that you are debugging E110,, is that using chipscope or
> other mean?
> if it using chipscope ,can you tell me the steps i follow when using
> chipscope ,,as all i read about chipscope assuming working on
> development boards so it generates the stimuli signals for the test core
> on the fpga .... which isn't the case for E1XX family
>
> Thanks in advance
>
> Ahmed
>
> On Sat, Apr 14, 2012 at 8:39 AM, xi yang <[email protected]> wrote:
>
>> Hi, all
>>
>> I create some FPGA codes for E110. For testing perpose?I want to use
>> XILINX Platform Cable to capture some output signals. But now, I cannot
>> find any JTAG ports on the motherboard (the J50 is empty, which is used for
>> debug on E100). Is there anybody know how to use XILINX Platform Cable for
>> FPGA test on E110? Please give me some advices. Thanks a lot!
>>
>>
>> _______________________________________________
>> USRP-users mailing list
>> [email protected]
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/attachments/20120414/857ee485/attachment-0001.html>
------------------------------
_______________________________________________
USRP-users mailing list
[email protected]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
End of USRP-users Digest, Vol 20, Issue 15
******************************************
