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Today's Topics:
1. Re: badd allocation, crashes and weird symbols (Josh Blum)
2. B100 schematics publicly available (Balint Seeber)
3. USRP N210 (or NI 2921) FPGA modification. (Seogoo Lee)
4. using messages. (Juan Daniel Fernandez Martinez)
5. Re: USRP N210 (or NI 2921) FPGA modification. (Matt Ettus)
6. Re: USRP N210 (or NI 2921) FPGA modification. (Seogoo Lee)
7. Re: USRP N210 (or NI 2921) FPGA modification. (Marcus D. Leech)
8. Re: USRP N210 (or NI 2921) FPGA modification. (Seogoo Lee)
9. Re: USRP N210 (or NI 2921) FPGA modification. (Marcus D. Leech)
10. overflow managment (raboteauo)
11. Re: USRP SBX daughter board (Matt Ettus)
12. Re: USRP SBX daughter board (Usrp IITM)
13. Simulation round_sd.v module block encounters errors
(Florian Schlembach)
----------------------------------------------------------------------
Message: 1
Date: Mon, 17 Dec 2012 12:34:25 -0600
From: Josh Blum <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] badd allocation, crashes and weird symbols
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1
On 12/17/2012 08:09 AM, Marco Rao wrote:
> Hello everybody!
>
> I am trying to run the examples provided with the UHD installer, in
> particular tx_waveforms.cpp. My configuration is: - msvc 9.0 -
> boostpro 1.47, multithread debug and release for both 9.0 and 10.0 (I
> also tried 9.0 only) plus unit test libraries - uhd, last available
> precompiled release 003.005.000
>
> I manage to compile and link the files but I get runtime errors like:
> - bad allocation - windows error message (application stopped
> working) --> this is the most frequent - ValueError: invalid args
> string (weird characters)
>
> this does not happen when I run the precompiled exe files provided
> with uhd installer, using the same input string. Moreover, I get an
> error when free.c is called if I run debug, but I guess this is due
> to the fact that uhd is compiled for release only. I read a few
> topics on this, but I did not sort it out...
>
> Any idea?
Can you make sure that the client app is build with the same build mode
as the library. Like Debug/Release?
My first guess, its just a mismatch,
-josh
>
>
>
>
> _______________________________________________ USRP-users mailing
> list [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
------------------------------
Message: 2
Date: Mon, 17 Dec 2012 11:52:27 -0800
From: Balint Seeber <[email protected]>
To: [email protected]
Subject: [USRP-users] B100 schematics publicly available
Message-ID:
<capcb_2rg1_w7m6wn8jptb9cfe29a4v37wlmqm-petnp4qpj...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Dear all,
A quick message to let you know that the USRP B100
schematics<http://code.ettus.com/redmine/ettus/documents/25>can now be
found at:
http://code.ettus.com/redmine/ettus/projects/public/documents
Kind regards,
Balint
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Message: 3
Date: Mon, 17 Dec 2012 14:33:31 -0600
From: Seogoo Lee <[email protected]>
To: [email protected]
Subject: [USRP-users] USRP N210 (or NI 2921) FPGA modification.
Message-ID:
<CAGpKNJR6xKummGN0=gU1jTJjYyb5uwkzuNMu2Hq83=gmkn7...@mail.gmail.com>
Content-Type: text/plain; charset=ISO-8859-1
Hi,
I need to modify FPGA verilog code for my project. What I want to do
is to add a simple correlation based frame synchronization on FPGA and
to change the internal timer of USRP after the frame synchronization
directly in FPGA.
My modification will be done between ddc and vita_rx_chain and I don't
want to touch uhd driver.
Do you think it is possible?
My USRPs are N210 (and NI 2921) and I first want to simulate the USRP
top verilog code before I build an FPGA image.
Is there any working environment for FPGA simulation?
I installed iverilog and simply tried to run
/testbench/single_u2_sim.v by 'make single'.
But it seems that some file links in cmdfile are broken, and,
moreover, it's only for usrp2, not for N210.
Please let me know your opinion.
Thank you.
Seogoo
------------------------------
Message: 4
Date: Mon, 17 Dec 2012 21:19:53 +0000
From: Juan Daniel Fernandez Martinez <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] using messages.
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
Hi everyone,
I am trying to implement "Messages" in a block that will be used for control.
Right now I have two sources of information about that.
The first one:
https://github.com/guruofquality/grextras/wiki/Blocks-Coding-Guide#wiki-messages
explains how messages work (got it) and gives some kind o example that hasn't
been that helpful for me (is not a full example, leaves some things for granted
that I am not getting).
The second one is: http://www.ruby-forum.com/topic/4405911, in this, the code
needed for building the messages is more explicit, the problem is that is not
an example, is a question about something that is not working with an
implementation of messages.
If someone knows about documentation and/or examples of how to use messages, I
would be really grateful
thanks
________________________________
Este documento puede contener informaci?n privilegiada o confidencial. Por
tanto, usar esta informaci?n y sus anexos para prop?sitos ajenos a los de la
Universidad Icesi, divulgarla a personas a las cuales no se encuentre destinado
este correo o reproducirla total o parcialmente, se encuentra prohibido en
virtud de la legislaci?n vigente. La universidad no asumir? responsabilidad
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posteriormente b?rrelo de su sistema sin conservar copia del mismo.
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Message: 5
Date: Mon, 17 Dec 2012 14:09:46 -0800
From: Matt Ettus <[email protected]>
To: Seogoo Lee <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] USRP N210 (or NI 2921) FPGA modification.
Message-ID:
<CAN=1kn8sBsfC8e17+otpmy+DBZi1Qop0KpGB=L=f22omajk...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Seogoo,
Your application sounds very reasonable and should be possible. We no
longer do full chip simulations of the design, as we found them to be too
slow and not helpful in debugging problems. Instead, we simulate the
individual components, which is why you will see a lot of smaller "_tb.v"
files.
Matt
On Mon, Dec 17, 2012 at 12:33 PM, Seogoo Lee <[email protected]> wrote:
> Hi,
>
> I need to modify FPGA verilog code for my project. What I want to do
> is to add a simple correlation based frame synchronization on FPGA and
> to change the internal timer of USRP after the frame synchronization
> directly in FPGA.
> My modification will be done between ddc and vita_rx_chain and I don't
> want to touch uhd driver.
> Do you think it is possible?
>
> My USRPs are N210 (and NI 2921) and I first want to simulate the USRP
> top verilog code before I build an FPGA image.
> Is there any working environment for FPGA simulation?
> I installed iverilog and simply tried to run
> /testbench/single_u2_sim.v by 'make single'.
> But it seems that some file links in cmdfile are broken, and,
> moreover, it's only for usrp2, not for N210.
>
> Please let me know your opinion.
>
> Thank you.
>
> Seogoo
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
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------------------------------
Message: 6
Date: Mon, 17 Dec 2012 17:55:17 -0600
From: Seogoo Lee <[email protected]>
To: Matt Ettus <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] USRP N210 (or NI 2921) FPGA modification.
Message-ID:
<CAGpKNJQwzMxE9XLJ0+DPB-4+cGnUyFgjBr2OmetzLypND=p...@mail.gmail.com>
Content-Type: text/plain; charset=ISO-8859-1
Hi Matt,
Thank you for your reply.
There is no testbench for ddc, but I think I can make it from rx_frontend_tb.v.
And, what is the format of the input and output data from ddc?
I think they are definitely fixed point data, but among 24 bits from
ADC, how many bits are used as fractional bits and integer bits?
I want to know the mapping from the fixed point data to the floating
point data that I can see in SW like GNU Radio or LabVIEW.
Thank you.
Seogoo
On Mon, Dec 17, 2012 at 4:09 PM, Matt Ettus <[email protected]> wrote:
>
> Seogoo,
>
> Your application sounds very reasonable and should be possible. We no
> longer do full chip simulations of the design, as we found them to be too
> slow and not helpful in debugging problems. Instead, we simulate the
> individual components, which is why you will see a lot of smaller "_tb.v"
> files.
>
> Matt
>
>
> On Mon, Dec 17, 2012 at 12:33 PM, Seogoo Lee <[email protected]> wrote:
>>
>> Hi,
>>
>> I need to modify FPGA verilog code for my project. What I want to do
>> is to add a simple correlation based frame synchronization on FPGA and
>> to change the internal timer of USRP after the frame synchronization
>> directly in FPGA.
>> My modification will be done between ddc and vita_rx_chain and I don't
>> want to touch uhd driver.
>> Do you think it is possible?
>>
>> My USRPs are N210 (and NI 2921) and I first want to simulate the USRP
>> top verilog code before I build an FPGA image.
>> Is there any working environment for FPGA simulation?
>> I installed iverilog and simply tried to run
>> /testbench/single_u2_sim.v by 'make single'.
>> But it seems that some file links in cmdfile are broken, and,
>> moreover, it's only for usrp2, not for N210.
>>
>> Please let me know your opinion.
>>
>> Thank you.
>>
>> Seogoo
>>
>> _______________________________________________
>> USRP-users mailing list
>> [email protected]
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
------------------------------
Message: 7
Date: Mon, 17 Dec 2012 19:02:41 -0500
From: "Marcus D. Leech" <[email protected]>
To: Seogoo Lee <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] USRP N210 (or NI 2921) FPGA modification.
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
> Hi Matt,
>
> Thank you for your reply.
>
> There is no testbench for ddc, but I think I can make it from
> rx_frontend_tb.v.
> And, what is the format of the input and output data from ddc?
> I think they are definitely fixed point data, but among 24 bits from
> ADC, how many bits are used as fractional bits and integer bits?
> I want to know the mapping from the fixed point data to the floating
> point data that I can see in SW like GNU Radio or LabVIEW.
>
> Thank you.
>
> Seogoo
>
>
All the arithmetic in the FPGA uses twos-complement integers. The VITA
packetizer turns that into 8-bit or 16-bit integers for wire-transmission
over the Ethernet connection. The host-side driver converts that as
appropriate into single-precision floating-point, or retains the
wire-format,
depending on how the "streamer" is configured on the host side.
--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
------------------------------
Message: 8
Date: Mon, 17 Dec 2012 21:43:45 -0600
From: Seogoo Lee <[email protected]>
To: "Marcus D. Leech" <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] USRP N210 (or NI 2921) FPGA modification.
Message-ID:
<CAGpKNJSiV1Coqt_E5+nF2Jt41=x6sT8KWPwKN=kgq_imnkt...@mail.gmail.com>
Content-Type: text/plain; charset=ISO-8859-1
Thank you, Marcus.
Your reply is very useful. But it is still unclear to me how the 16
bits integer numbers can be converted single precision floating point
numbers.
For example, if the received data is 0.01 from uhd host-side driver
with single precision floating point presentation, what is the
corresponding 16 bits integer data from ddc_chain in FPGA?
Thank you.
Seogoo
On Mon, Dec 17, 2012 at 6:02 PM, Marcus D. Leech <[email protected]> wrote:
>> Hi Matt,
>>
>> Thank you for your reply.
>>
>> There is no testbench for ddc, but I think I can make it from
>> rx_frontend_tb.v.
>> And, what is the format of the input and output data from ddc?
>> I think they are definitely fixed point data, but among 24 bits from
>> ADC, how many bits are used as fractional bits and integer bits?
>> I want to know the mapping from the fixed point data to the floating
>> point data that I can see in SW like GNU Radio or LabVIEW.
>>
>> Thank you.
>>
>> Seogoo
>>
>>
> All the arithmetic in the FPGA uses twos-complement integers. The VITA
> packetizer turns that into 8-bit or 16-bit integers for wire-transmission
> over the Ethernet connection. The host-side driver converts that as
> appropriate into single-precision floating-point, or retains the
> wire-format,
> depending on how the "streamer" is configured on the host side.
>
>
>
>
> --
> Marcus Leech
> Principal Investigator
> Shirleys Bay Radio Astronomy Consortium
> http://www.sbrac.org
>
>
------------------------------
Message: 9
Date: Mon, 17 Dec 2012 22:49:35 -0500
From: "Marcus D. Leech" <[email protected]>
To: Seogoo Lee <[email protected]>, "[email protected]"
<[email protected]>
Subject: Re: [USRP-users] USRP N210 (or NI 2921) FPGA modification.
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1
On 17/12/12 10:43 PM, Seogoo Lee wrote:
> Thank you, Marcus.
>
> Your reply is very useful. But it is still unclear to me how the 16
> bits integer numbers can be converted single precision floating point
> numbers.
> For example, if the received data is 0.01 from uhd host-side driver
> with single precision floating point presentation, what is the
> corresponding 16 bits integer data from ddc_chain in FPGA?
>
> Thank you.
>
> Seogoo
>
Well, the wire format is signed 16-bit integers, so when UHD receives
it, it simply divides the
value by 32768, giving a floating point value.
In your case, 0.01 * 32768 = 328 as an integer
--
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
------------------------------
Message: 10
Date: Tue, 18 Dec 2012 08:12:37 +0100
From: raboteauo <[email protected]>
To: [email protected]
Subject: [USRP-users] overflow managment
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
Hi,
when UHD library detects an overflow, can we use the metadata time stamp
in order to compute the number of losted samples ?
Thanks.
Olivier
------------------------------
Message: 11
Date: Mon, 17 Dec 2012 23:33:48 -0800
From: Matt Ettus <[email protected]>
To: Usrp IITM <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] USRP SBX daughter board
Message-ID:
<CAN=1kn_8peXR2Z8iJ_6N=132bffn7fxxxzxpmdj3hzlcynt...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
The SBX has controllable gain on TX as well as RX. How did you set the
gain? Are you able to see anything on an FFT display?
Matt
On Thu, Dec 13, 2012 at 11:12 PM, Usrp IITM <[email protected]>wrote:
> We are trying to implement OFDM point to point link using USRPN210. The
> frequency used is 2.49GHz. When we used RFX2400 daughter board in
> transmitter ,it works for rate of 5MHz for a Rx gain of 40dB-50dB. But when
> we use SBX daughter board(which has variable transmit gain), it doesn't
> work for 5 MHz rate.We can't even see a spectrum in the reciever.Can
> someone explain how to adjust the gain for different rates and all other
> specifications of SBX daughterboard.
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 12
Date: Tue, 18 Dec 2012 17:02:56 +0530
From: Usrp IITM <[email protected]>
To: Matt Ettus <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] USRP SBX daughter board
Message-ID:
<CAPkh=_9mwea_hu78mqujh5jwhqvkb9axyzxhyxseeyz6tew...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi Matt,
We are able to see the spectrum now. There was some small bug.
However the carrier is being transmitted by the SBX board. We have a
transmit filter that has a notch at DC, so technically the data has no DC
component (before being sent to the USRP). The carrier is absent when we
use the RFX2400 board to transmit. We are using a centre frequency of 2.49
Ghz and receiving with an RFX2400 board. Please see the attached pictures.
RFX2400 TX
[image: Inline image 1]
*SBX* *TX*
[image: Inline image 2]
Any suggestion as to why this is happening?
-Regards
RK
On Tue, Dec 18, 2012 at 1:03 PM, Matt Ettus <[email protected]> wrote:
>
> The SBX has controllable gain on TX as well as RX. How did you set the
> gain? Are you able to see anything on an FFT display?
>
> Matt
>
>
> On Thu, Dec 13, 2012 at 11:12 PM, Usrp IITM <[email protected]>wrote:
>
>> We are trying to implement OFDM point to point link using USRPN210. The
>> frequency used is 2.49GHz. When we used RFX2400 daughter board in
>> transmitter ,it works for rate of 5MHz for a Rx gain of 40dB-50dB. But when
>> we use SBX daughter board(which has variable transmit gain), it doesn't
>> work for 5 MHz rate.We can't even see a spectrum in the reciever.Can
>> someone explain how to adjust the gain for different rates and all other
>> specifications of SBX daughterboard.
>>
>>
>> _______________________________________________
>> USRP-users mailing list
>> [email protected]
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>>
>
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------------------------------
Message: 13
Date: Tue, 18 Dec 2012 13:12:41 +0100
From: Florian Schlembach <[email protected]>
To: [email protected]
Subject: [USRP-users] Simulation round_sd.v module block encounters
errors
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
I am currently trying to simulate my module. I am reusing the round_sd.v
module block that is rounding the sample value at the end of the ddc chain:
http://www.upload-pictures.de/bild.php/21491,usrpn210analysisofddcchainF9AEW.jpg
I instantiate it via:
round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i
(.clk(clock),.reset(reset),
.in(i_sq[23:0]),.strobe_in(strobe_round), .out(i_sq_round),
.strobe_out(strobe_cu));
I don't get any output on i_sq_round, only 16'bx. As I followed the
instantiation chain of round_sd, I figured out that the following line
wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
is not working in simulation because there is a sum of any valid bits of
in1 with x-states, resulting in 24'bx of sum_int and ending up in
i_sq_round being 16'bx.
I reckon that it apparently seems to work on hardware because x-states
doesn't exist there. What can I do to get it run in simulation (using ISim)?
BR, Flo
------------------------------
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------------------------------
End of USRP-users Digest, Vol 28, Issue 17
******************************************
