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Today's Topics:
1. Re: Simulation round_sd.v module block encounters errors
(Matt Ettus)
2. Re: Simulation round_sd.v module block encounters errors
(Matt Ettus)
----------------------------------------------------------------------
Message: 1
Date: Sat, 19 Jan 2013 12:58:51 -0800
From: Matt Ettus <[email protected]>
To: Florian Schlembach <[email protected]>
Cc: "[email protected]" <[email protected]>, Florian
Schlembach
<[email protected]>,
"[email protected]"
<[email protected]>
Subject: Re: [USRP-users] Simulation round_sd.v module block
encounters errors
Message-ID:
<CAN=1kn8S9-p=GwmDfUaHN7Uk=p25whpocnc9q9wumyjz-v_...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
err is assigned in line 21 -- it is an output from round. The sign-ext
block extends that.
Matt
On Mon, Jan 7, 2013 at 7:25 AM, Florian Schlembach <
[email protected]> wrote:
> To get it to simulate properly, set the initial values of the registers
>> where they are defined, like this:
>>
>> reg [15:0] myreg = 0;
>>
>> Matt
>>
>>
> Matt, for sure thats right. Actually, considering the example of
> round_sd.v it is not obvious to me where the register err gets any value?
> It is initialized in line 13 but no value is assigned?
>
> See http://code.ettus.com/redmine/**ettus/projects/uhd/repository/**
> revisions/master/entry/fpga/**usrp2/sdr_lib/round_sd.v<http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/usrp2/sdr_lib/round_sd.v>
>
> If err_ext should be inserted into module add2_and_clip_reg in line 19,
> how is err_ext being calculated via the macro sign_extend in line 16?
>
> To me, it seems that the sign_extend module instantiation is redundant
> here?
>
>
>
>
>
> ______________________________**_________________
> USRP-users mailing list
> [email protected]
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>
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Message: 2
Date: Sat, 19 Jan 2013 12:58:51 -0800
From: Matt Ettus <[email protected]>
To: Florian Schlembach <[email protected]>
Cc: "[email protected]" <[email protected]>, Florian
Schlembach
<[email protected]>,
"[email protected]"
<[email protected]>
Subject: Re: [USRP-users] Simulation round_sd.v module block
encounters errors
Message-ID:
<CAN=1kn8S9-p=GwmDfUaHN7Uk=p25whpocnc9q9wumyjz-v_...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
err is assigned in line 21 -- it is an output from round. The sign-ext
block extends that.
Matt
On Mon, Jan 7, 2013 at 7:25 AM, Florian Schlembach <
[email protected]> wrote:
> To get it to simulate properly, set the initial values of the registers
>> where they are defined, like this:
>>
>> reg [15:0] myreg = 0;
>>
>> Matt
>>
>>
> Matt, for sure thats right. Actually, considering the example of
> round_sd.v it is not obvious to me where the register err gets any value?
> It is initialized in line 13 but no value is assigned?
>
> See http://code.ettus.com/redmine/**ettus/projects/uhd/repository/**
> revisions/master/entry/fpga/**usrp2/sdr_lib/round_sd.v<http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/usrp2/sdr_lib/round_sd.v>
>
> If err_ext should be inserted into module add2_and_clip_reg in line 19,
> how is err_ext being calculated via the macro sign_extend in line 16?
>
> To me, it seems that the sign_extend module instantiation is redundant
> here?
>
>
>
>
>
> ______________________________**_________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/**mailman/listinfo/usrp-users_**lists.ettus.com<http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com>
>
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