Send USRP-users mailing list submissions to
[email protected]
To subscribe or unsubscribe via the World Wide Web, visit
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
or, via email, send a message with subject or body 'help' to
[email protected]
You can reach the person managing the list at
[email protected]
When replying, please edit your Subject line so it is more specific
than "Re: Contents of USRP-users digest..."
Today's Topics:
1. FPGA documentation (Fernando Quivira)
----------------------------------------------------------------------
Message: 1
Date: Sat, 2 Feb 2013 18:17:31 -0500
From: Fernando Quivira <[email protected]>
To: [email protected]
Subject: [USRP-users] FPGA documentation
Message-ID:
<CAD6+UKK9pD17TnLO5z_RQF8-jyd=7qnrenqqtz4grofwsnr...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi everyone:
I'm trying to understand how the FPGA code works for the N210. More
specifically, I was reading the signal processing code in the sdr_lib
folder. Is there more documentation about this codes somewhere in the repo?
For example, I was looking at the add2.v file. It seems to me that this
code is adding two numbers and then dividing by two. Is that correct? Where
is that used? I have doubts like this for other parts of the code so that's
why I wanted to know about more documentation. I'd like to see why and how
the dsp blocks (cordic, cic, etc) are implemented
Thanks
- Fernando
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/attachments/20130202/d2e5a5da/attachment-0001.html>
------------------------------
Subject: Digest Footer
_______________________________________________
USRP-users mailing list
[email protected]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
------------------------------
End of USRP-users Digest, Vol 30, Issue 3
*****************************************
