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Today's Topics:
1. power_trig (dave)
2. Re: power_trig (dave)
3. Any significant difference between SBX, WBX for 434MHz?
(Sivan Toledo)
4. UHD TX Streamer Metadata (Tim Schuschies)
5. Re: Any significant difference between SBX, WBX for 434MHz?
(Marcus D. Leech)
----------------------------------------------------------------------
Message: 1
Date: Sun, 10 Mar 2013 23:45:12 +0000
From: dave <[email protected]>
To: [email protected]
Subject: [USRP-users] power_trig
Message-ID: <[email protected]>
Content-Type: text/plain; charset="UTF-8"
I'm trying to make a custom module after the DDC based on power_trig. If
successful, will the bb_strobe serve to regulate which blocks of IF get
sent back to the host over the ethernet? Will each group get tagged
with a vita time and data size stamp? If so, how can I get at these on
the host side?
experimentation so far:
1. confirmed that ISE v14.4 could compile the unmodified program. That
worked fine.
2. added in the custom_dsp_rx provisions. It compiled with errors:
ERROR:HDLCompiler:806 - .../uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v" Line
66: Syntax error near "#".
:
ERROR:ProjectMgmt - 2 error(s) found while parsing design hierarchy.
it doesn't like something about
`RX_DSP1_MODULE #(.WIDTH(WIDTH)) rx_dsp1_custom (...
but even with the error the image worked as expected, just the same as
the unmodified image.
3. removed custom_dsp_rx and added in power_trig
It compiled with the same error but the image loads and runs ort of.
I expected to get a bunch of disjointed IF segments run together.
Instead I get all zeros corresponding to the entire recording time.
Sending in different thresh values with set_user_register (is this
right) doesn't make any difference.
4. I tried to debug with the power_trig_tb but am new to verilog and
ISE and can't get anything but xs on the output. The testbench doesn't
quite match the power_trig.v format, it tries to set run and this
version of power_trig doesn't have that parameter so I just removed it.
Maybe I'm missing a link to something that the module would see in the
full program.
Any ideas?
------------------------------
Message: 2
Date: Mon, 11 Mar 2013 02:58:06 +0000
From: dave <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] power_trig
Message-ID: <[email protected]>
Content-Type: text/plain; charset="UTF-8"
update: I think I fixed the syntax error, WIDTH is a parameter not an
input, so I removed the #(.WIDTH(WIDTH)) reference from the line with
the error. Two hours later (testbenching is next on the to-learn list) it
compiles with a message about timing:
Process "Generate Programming File" completed successfully
INFO:TclTasksC:1850 - process run : Generate Programming File is done.
touch /home/dave/uhd/fpga/usrp2/top/N2x0/build-N210R3_ptrig/u2plus.bin
python /home/dave/uhd/fpga/usrp2/top/python/check_timing.py
/home/dave/uhd/fpga/usrp2/top/N2x0/build-N210R3_ptrig/u2plus.twr
Derived Constraint Report
Derived Constraints for TS_clk_fpga_p
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period
| Timing Errors | Paths Analyzed |
| Constraint | Requirement
|-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative
| Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_fpga_p | 10.000ns| 4.800ns|
12.320ns| 0| 63| 6| 1651716|
| TS_dcm_out | 10.000ns| 12.320ns|
N/A| 63| 0| 1223313| 0|
| TS_clk270_100 | 10.000ns| 1.248ns|
N/A| 0| 0| 0| 0|
| TS_clk_div | 20.000ns| 18.081ns|
N/A| 0| 0| 428403| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
1 constraint not met.
Maybe that's the reason for returning all 0s.
I'll probably figure that out, the main question is how to get the
time-stamped IF blocks on the PC side.
Thanks!
> On Sun, 2013-03-10 at 23:45 +0000, dave wrote:
> > I'm trying to make a custom module after the DDC based on power_trig. If
> > successful, will the bb_strobe serve to regulate which blocks of IF get
> > sent back to the host over the ethernet? Will each group get tagged
> > with a vita time and data size stamp? If so, how can I get at these on
> > the host side?
> >
> >
> > experimentation so far:
> > 1. confirmed that ISE v14.4 could compile the unmodified program. That
> > worked fine.
> > 2. added in the custom_dsp_rx provisions. It compiled with errors:
> > ERROR:HDLCompiler:806 - .../uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v" Line
> > 66: Syntax error near "#".
> > :
> > ERROR:ProjectMgmt - 2 error(s) found while parsing design hierarchy.
> >
> > it doesn't like something about
> > `RX_DSP1_MODULE #(.WIDTH(WIDTH)) rx_dsp1_custom (...
> >
> > but even with the error the image worked as expected, just the same as
> > the unmodified image.
> >
> > 3. removed custom_dsp_rx and added in power_trig
> >
> > It compiled with the same error but the image loads and runs ort of.
> > I expected to get a bunch of disjointed IF segments run together.
> > Instead I get all zeros corresponding to the entire recording time.
> > Sending in different thresh values with set_user_register (is this
> > right) doesn't make any difference.
> >
> > 4. I tried to debug with the power_trig_tb but am new to verilog and
> > ISE and can't get anything but xs on the output. The testbench doesn't
> > quite match the power_trig.v format, it tries to set run and this
> > version of power_trig doesn't have that parameter so I just removed it.
> > Maybe I'm missing a link to something that the module would see in the
> > full program.
> >
> > Any ideas?
>
------------------------------
Message: 3
Date: Mon, 11 Mar 2013 13:54:22 +0200
From: Sivan Toledo <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] Any significant difference between SBX, WBX for
434MHz?
Message-ID:
<caol_rufwq8v1bsv88_h+xhp71dqmox37vrcplkmftwd-bl-...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi,
I am going to purchase a few more N200's with either an SBX or a WBX, to
use on 434MHz. So far I've been using the WBX with good results.
Will there be any significant difference between the two RF boards on that
frequency (both cover it)?
Thanks, Sivan
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Message: 4
Date: Mon, 11 Mar 2013 13:15:17 +0100
From: Tim Schuschies <[email protected]>
To: [email protected]
Subject: [USRP-users] UHD TX Streamer Metadata
Message-ID:
<caov+zhtsfca48n_n559rrlh47bdbmj4nnqjugvwrbsagzhl...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi All,
I'm trying to extend the metadata of UHD's tx_streamer. I want to transmit
some further data to my N210 and I thought that the metadata would be a
possibility. But now I'm lost in following their path. I don't find the
point where a tx packet is sent by the uhd driver to the USRP. I think it
is somewhere in the "send_one_packet" function or in the
"converter_thread_task". I've also seen that the metadata are copied to
another structure called "if_packet_info". In this structure there is a
variable which represents the maximum number of 32bit words this structure
contains. So I have some questions:
1) Is it possible to change this value without damaging the driver?
2) Is it possible to transmit more metadata to the USRP at all?
3) And where can I find the handling of that metadata in the ZPU firmware
of my N210?
4) Where is a TX packet sent to the USRP within the UHD drivers?
Thanks
Tim
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------------------------------
Message: 5
Date: Mon, 11 Mar 2013 11:24:58 -0400
From: "Marcus D. Leech" <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] Any significant difference between SBX, WBX
for 434MHz?
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
On 03/11/2013 07:54 AM, Sivan Toledo wrote:
> Hi,
>
> I am going to purchase a few more N200's with either an SBX or a WBX,
> to use on 434MHz. So far I've been using the WBX with good results.
>
> Will there be any significant difference between the two RF boards on
> that frequency (both cover it)?
>
> Thanks, Sivan
>
I wouldn't expect any major differences between the two cards at that
frequency range.
--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
------------------------------
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