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Today's Topics:

   1. Re: OFDM Implementation Error (Josh Blum)
   2. Re: Using Metadata (Josh Blum)


----------------------------------------------------------------------

Message: 1
Date: Sun, 17 Mar 2013 13:32:20 -0500
From: Josh Blum <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] OFDM Implementation Error
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1



On 03/17/2013 05:25 AM, ZaInzAiN Jj wrote:
> I use latest gnuradio 3.6.4, USRP N210, Ubuntu 12.04
> I try,
> 
> root@pasca:/usr/local/src/gnuradio-3.6.4/gr-digital/examples/ofdm# 
> ./benchmark_tx.py 
> 
> but there are error as below
> Traceback (most recent call last):
>   File "./benchmark_tx.py", line 29, in <module>
>     from gnuradio import digital
> ImportError: cannot import name digital
> 
> What is the trouble?

I would guess that your PYTHONPATH is not set or the gnuradio.digital
module is not installed.

-josh

> 
> Thanks,
> 
> 
> Zai
> 
> 
> 
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> 



------------------------------

Message: 2
Date: Sun, 17 Mar 2013 13:39:21 -0500
From: Josh Blum <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] Using Metadata
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1



On 03/16/2013 07:04 AM, Tim Schuschies wrote:
> Hi All,
> I am still trying to use the metadata of the tx-streamer. I know that I
> probably can use the CID field because it's not used yet. Implementing that
> in UHD seems not to be problem. I've already done this. But now I'm at a
> point I simply do not know how to go on. The problem is that I still don't
> know how I can use the data of the VRT header within my FPGA design. I
> tried to find the data by sending a known value to USRP and observing the
> signals I thought that they could probably contain these data. I observed
> all outputs of the VITA_TX_DEFRAMER with a debugger. I don't find anything
> useful. It's still quite important for me to get this work.
> Can anyone help me, please?
> Is the processing of the CID field already implemented?
> Which are the signals the data are assigned to?
> Is it possible to assign the 64bit CID field to a 64bit wide bus in the
> FPGA?
> If yes, how can do this?
> Can anyone explain how the VITA_TX_DEFRAMER works? I tried to understand
> it, but I don't get it...
> 

It might be easy for you to just pack your custom data into some of the
samples; and then pull them out before the vita deframer.

* Put a custom block into the FPGA plumbing, before the tx VITA chain
* In this custom block, separate the custom data, dont forward it

These are the 32 bit wide fifo signals going to the vita chain in
u2plus_core.v .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy),
.tx_dst_rdy_o(tx_dst_rdy),

Rules for the fifo signals:
http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/usrp2/fifo/fifo_spec.txt

-josh

> Thanks a lot.
> Tim
> 
> 
> 
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> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> 



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