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Today's Topics:
1. Frequency Offsets for USRP -N210 (mahaveer gupta)
2. Testbench for usrp2 (Purush)
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Message: 1
Date: Wed, 15 May 2013 02:03:19 -0400
From: mahaveer gupta <[email protected]>
To: [email protected]
Subject: [USRP-users] Frequency Offsets for USRP -N210
Message-ID:
<CAMhWHyYvLWhLOiB9y1SNh0=3rwa58v0oaza8gkdxe9gecpd...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hello,
The frequency offset computed for a a pair of USRP-N210's comes out to
be different every time
Frequency offsets usually vary in longer timescales but I get completely
non-correlated values every time I make transmissions between a
transmitter-receiver pair.
When I sent back-to-back packets, the offset estimation from different
preambles deviate as big as 30-40%. Is this the expected behavior? Will
appreciate if somebody can help me figure out whats going on here?
Wondering whether there is a way to calibrate the USRP such that the
frequency offset does not vary in shorter time-scales
Thanks,
M
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Message: 2
Date: Wed, 15 May 2013 11:20:01 +0200
From: Purush <[email protected]>
To: [email protected]
Subject: [USRP-users] Testbench for usrp2
Message-ID:
<CAOUk5sAk4xFsT=7vjp-2w1ussyzq1pa3n6nmjqzve54prd+...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
I am USRP newbie. I am trying to get a first hands on experience in adding
few registers into the FPGA and reading them back into the host machine.
I am using USRP2 and using the main branch of UHD.
To start with I am just adding registers into the "u2_core.v" and making
changes into the firmware of ZPU. I added to the code to write
"sr_my_regs_ctrl->params_b
= 0xffffffff;" to the zpu code (in the u2_init.c file) and generated the
rom file. As described in :
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2011-March/000886.html
I renamed the generated ROM file to "flash.rom" and moved it to the
testbench folder.
I am using a mixed language simulator (i.e. ModelSim) to simulate the
design and see the register being written. I understand that the testbench
found in the "testbench/single_u2_sim.v" is outdated and needs to be
changed to remove some obvious library errors generated due to FIFO
libraries. As discussed in the message exchanges by the post:
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2012-January/003305.html
I do ensure that the "flash.rom" is read properly. I ran the simulation to
4000 us and yet the registers "sr_my_regs_ctrl->params_b" are not written
neither the LED registers show any changes.
Where is that I have gone wrong? Am I following the right steps here?
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End of USRP-users Digest, Vol 33, Issue 13
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