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Today's Topics:
1. Re: Testbench for usrp2 (Florian Schlembach)
----------------------------------------------------------------------
Message: 1
Date: Mon, 27 May 2013 15:10:23 +0200
From: Florian Schlembach <[email protected]>
To: [email protected]
Cc: [email protected]
Subject: Re: [USRP-users] Testbench for usrp2
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
On 05/24/2013 03:29 PM, Purush wrote:
> I was able to fix the testbench issue. The problem was in the
> initialization of with the 'ram_loader.v'. There was a single bit
> shift when the program file was loaded in to the design. I played with
> the clock of the 'single_u2_sim.v' design. (As i didn't want too many
> changes in the actual design itself)
>
> I finally edited the 'aux_clk' to:
>
> always #12 aux_clk = ~aux_clk;
>
> This corrected the problem.
>
> Now the design has my custom registers connected to settings_reg. The
> reading of this register is enabled by connecting the outputs of the
> register to an empty space in the readback_mux.
>
> I want to read the registers from the host machine. 'multi_usrps.hpp'
> has a function to write the register ...which goes something like
> 'usrp->set_user_register(240,0,0);'
>
> Now the question is : how do I read the register connected to the
> 'readback_mux' from the host machine?
>
I don't get your exact point but the user registers can be transmitted
in a pretty convenient way from the host machine to the FPGA modules.
You are already on the right path.
usrp->set_user_register(240,0,0) sends a 0 on address 240 to the usrp
with motherboard id 0. Here's the USRP code I copied from a GNU Radio
UHD source module:
void set_user_register(const uint8_t addr, const uint32_t data,
size_t mboard){
#ifdef UHD_USRP_MULTI_USRP_USER_REGS_API
_dev->set_user_register(addr, data, mboard);
#else
throw std::runtime_error("not implemented in this version");
#endif
}
Thus, the address space is 8-bit wide and the data word is 32-bit wide.
That's it from the host PC side.
On the FPGA code side, the user registers are distributed over most of
the sub-modules. Have a look into the u2plus_core.v, lines 179-181:
wire [7:0] set_addr, set_addr_dsp, set_addr_user;
wire [31:0] set_data, set_data_dsp, set_data_user;
wire set_stb, set_stb_dsp, set_stb_user;
The latter *_user are the wires that come from the set_user_register UHD
API command. From your FPGA modules, you can retrieve them, e.g. by
//settings bus
always @(posedge clock) begin
if(set_stb_user) begin
case(set_addr_user)
1: flag_setting1 <= set_data_user[0];
2: flag_setting2 <= set_data_user[0];
endcase
end
end
HTH, Flo
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