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Today's Topics:
1. Re: Something about B210 board (Ian Buckley)
2. TX/RX Switch on SBX Daughterboard in Full Duplex mode
(Tuerkyilmaz, Eral)
3. RX timeout after longer inactivity (Ales Povalac)
4. LFM tx/rx question with N210/WBX combo ([email protected])
5. Re: LFM tx/rx question with N210/WBX combo (Marcus M?ller)
6. Custom FPGA build for N200R4 (Juha Vierinen)
7. Re: Something about B210 board (Michael West)
8. Re: RX timeout after longer inactivity (Michael West)
9. Re: Custom FPGA build for N200R4 (Juha Vierinen)
10. UHD & B210 board (=?ISO-8859-1?B?NDQyNzc3ODE2?=)
11. Re: B2XX USB 3.0 PCI Express Card Compatibility/Suggestions
(James Balean)
----------------------------------------------------------------------
Message: 1
Date: Wed, 5 Mar 2014 09:40:15 -0800
From: Ian Buckley <[email protected]>
To: 442777816 <[email protected]>
Cc: USRP-users <[email protected]>
Subject: Re: [USRP-users] Something about B210 board
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
You can pull the latest source code for both the FPGA RTL and the Host based
API and example applications from:
https://github.com/EttusResearch/uhd
The current public release version is UHD 3.7.0.
To build for B210, in a shell environment already setup for a versions of
Xilinx ISE14.4 or newer:
cd INSTALL_ROOT/uhd/fpga/usrp3/top/b200
make B210
When the build is complete you will be able to find the .bin and .bit files, as
well as report files in the directory:
INSTALL_ROOT/uhd/fpga/usrp3/top/b200/build-B200
B200/B210 share a common PCB schematic and RTL FPGA design.
-Ian
On Mar 5, 2014, at 5:36 AM, 442777816 <[email protected]> wrote:
> Hi,all
> I met some problems about my B210 board.
> 1. The fpga source downloaded from ettus.com just only contained sth named
> B200,is it same with the sources of B210? And is the schematic fit for B210
> board?
> I established a project by ISE and compiled it ,but when I run the example
> rx_samples_to_file, and it also shows that the .bin file in burned into B210
> successfully,but then some errors like below pop up.
> AssertionError:accum_timeout < _timeout
> in uint64_t radio_ctrl_core_3000_impl::wait_for_ack(bool)
> at ~/radio_ctrl_core_3000.cpp:234
>
> What should I do to establish a .bin on my own?
>
>
> 2.When I run the examples ,the code can identify the specific device ,right?
> And I guess the device is made by the make function in B210_impl.cpp file.But
> I couldn't find the inclusion relation, it seems that the B210_impl.cpp is
> not used at all!It does really confuse me..
> Can the latest UHD support changing the bandwidth of B210? If not ,can I
> modify it?
>
>
> Thank you very very much! :D
>
> Greeting,
> Chuang
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 2
Date: Wed, 5 Mar 2014 13:57:27 +0100
From: "Tuerkyilmaz, Eral" <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] TX/RX Switch on SBX Daughterboard in Full Duplex
mode
Message-ID:
<[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
Hello,
We will operate the USRP N210 in combination with the SBX board in a TDD mode.
For this we intend to use both RF connections (TX/RX (used for transmitting)
and RX2 (used for receiving)) and do the switching by an external circuit.
Therefore we want to provide the internal TX/RX switching signal to the
external circuit even when the antenna setting is "Full Duplex".
I observed that this is possible with the WBX board since it always switches
the signal on the pin io_tx_15 even when the receive antenna is set to "RX2"
(Full Duplex Mode).
I couldn't observe this behaviour on the SBX board. The TX/RX switch is only
switched when the antenna setting "TX/RX" is used. Is there any quick way to
change this behavior to the "WBX-style" from the UHD driver?
Thank you and the Best Regards,
Eral T?rkyilmaz
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Message: 3
Date: Wed, 5 Mar 2014 15:10:32 +0100
From: Ales Povalac <[email protected]>
To: usrp-users <[email protected]>
Subject: [USRP-users] RX timeout after longer inactivity
Message-ID:
<CADyMgmzemS06p=ufmcvhbuq74-+gfmccxtv0itgggwgvhcz...@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Dear all,
we have a problem with UHD RX code. If there is a delay between
get_rx_stream() and issue_stream_cmd() longer than ca. 64 seconds, the
recv() call always fails with ERROR_CODE_TIMEOUT.
Issue can be reproduced in rx_samples_to_file example by adding a
delay of >64 seconds before stream command, diff at
http://pastebin.com/MFDNVyYy . Threshold is near 64 seconds - 60 sec
always works, 70 sec always fails with "Timeout while streaming".
I am on maint branch of UHD, tested also on 003.005.001 with the same
result. Any ideas how to fix this issue?
Thanks,
Ales
------------------------------
Message: 4
Date: Wed, 5 Mar 2014 15:39:12 +0000 (UTC)
From: [email protected]
To: [email protected]
Subject: [USRP-users] LFM tx/rx question with N210/WBX combo
Message-ID:
<743655822.228574.1394033952972.javamail.r...@sz0114a.westchester.pa.mail.comcast.net>
Content-Type: text/plain; charset="utf-8"
Hello,
?
2 part question, probably similar answer :)
?
Is it possible to captude an LFM pulse (IQ samples) using the USRP N210 with
WBX daughtercard?
?
What I dont see how to do would be specifying the freq range when tuning since
you specify a center freq freq... Do you get it for free with the bandwidth
spec?
?
Similar question for tx side. API seems to want a specific freq and BW...
?
Any guidance or examples would be greatly appreciated.
?
Thanks,
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Message: 5
Date: Wed, 05 Mar 2014 19:53:19 +0100
From: Marcus M?ller <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] LFM tx/rx question with N210/WBX combo
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hi Tilla,
a little much whitespace ;) but:
> Is it possible to captude an LFM pulse (IQ samples) using the USRP
N210 with WBX daughtercard?
Of course. However, it is limited to the sampling bandwidth; you just
rx samples of that chirp (or whatever).
> What I dont see how to do would be specifying the freq range when
tuning since you specify a center freq freq... Do you get it for free
with the bandwidth spec?
Reception takes place from [-samplerate/2; +samplerate/2] around the
center frequency. It's an downmixing complex baseband receiver system.
> TX Side
yep. The sample rate defines your max. bandwidth.
Greetings,
Marcus
On 05.03.2014 16:39, [email protected] wrote:
>
>
>
>
>
> Hello,
>
>
>
>
>
> 2 part question, probably similar answer :)
>
>
>
>
>
> Is it possible to captude an LFM pulse (IQ samples) using the USRP
> N210 with WBX daughtercard?
>
>
>
>
>
> What I dont see how to do would be specifying the freq range when
> tuning since you specify a center freq freq... Do you get it for
> free with the bandwidth spec?
>
>
>
>
>
> Similar question for tx side. API seems to want a specific freq and
> BW...
>
>
>
>
>
> Any guidance or examples would be greatly appreciated.
>
>
>
>
>
> Thanks,
>
>
>
>
> _______________________________________________ USRP-users mailing
> list [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
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------------------------------
Message: 6
Date: Wed, 5 Mar 2014 21:40:02 +0000
From: Juha Vierinen <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] Custom FPGA build for N200R4
Message-ID:
<cagbkif3i62xap9pewq3m8evy-khcicjvcmgo7jgbovjajkm...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi,
I tried doing a custom_dsp_rx module based on the instructions on the git
source. I also found Tom Hartley's post useful, as the CUSTOM_DEFS caused
problems with the compiilation environment. I ended up using the "Verilog
Macros" "LVDS=1|RX_DSP0_MODULE=custom_dsp_rx" approach as suggested in
Tom's tutorial mail.
However, I still got an error related with missing BUF_SIZE parameter. I've
pretty much never programmed in verilog, but I am guessing that the API for
customizing the dsp chain is in a broken state at the moment.
I then went in and pretty much did the changes that I wanted directly in
ddc_chain.v. I'm trying to compile that right now. We'll see how that goes.
I'm using ISE 12.2, as suggested on the uhd web site.
juha
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Message: 7
Date: Wed, 5 Mar 2014 15:46:06 -0800
From: Michael West <[email protected]>
To: Ian Buckley <[email protected]>
Cc: USRP-users <[email protected]>
Subject: Re: [USRP-users] Something about B210 board
Message-ID:
<CAM4xKrqCX9QeYknnk63k18Noqb3w_T=x-zzc1jurot3h3na...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Chuang,
Setting the bandwidth for the B210 is on our list of improvements for UHD.
We are working on it. Keep an eye out for it in future releases.
If you can't wait for the feature to be released, you can make your own
changes to UHD to implement it. There is a place holder in the code for it
in ad9361_ctrl class called set_bw_filter(). Simply implement that
function and then you can call multi_usrp::set_rx_bandwidth() to set it.
Best regards,
Michael E. West
Senior Software Design Engineer
Ettus Research
www.ettus.com
On Wed, Mar 5, 2014 at 9:40 AM, Ian Buckley <[email protected]> wrote:
> You can pull the latest source code for both the FPGA RTL and the Host
> based API and example applications from:
> https://github.com/EttusResearch/uhd
> The current public release version is UHD 3.7.0.
>
> To build for B210, in a shell environment already setup for a versions of
> Xilinx ISE14.4 or newer:
> cd INSTALL_ROOT/uhd/fpga/usrp3/top/b200
> make B210
>
> When the build is complete you will be able to find the .bin and .bit
> files, as well as report files in the directory:
> INSTALL_ROOT/uhd/fpga/usrp3/top/b200/build-B200
>
> B200/B210 share a common PCB schematic and RTL FPGA design.
>
> -Ian
>
> On Mar 5, 2014, at 5:36 AM, 442777816 <[email protected]> wrote:
>
> Hi,all
> I met some problems about my B210 board.
> 1. The fpga source downloaded from ettus.com just only contained sth
> named B200,is it same with the sources of B210? And is the schematic fit
> for B210 board?
> I established a project by ISE and compiled it ,but when I run the
> example rx_samples_to_file, and it also shows that the .bin file in burned
> into B210 successfully,but then some errors like below pop up.
> *AssertionError:accum_timeout < _timeout*
> *in uint64_t radio_ctrl_core_3000_impl::wait_for_ack(bool)*
> *at ~/radio_ctrl_core_3000.cpp:234*
>
> What should I do to establish a .bin on my own?
>
>
> 2.When I run the examples ,the code can identify the specific device
> ,right? And I guess the device is made by the make function in
> B210_impl.cpp file.But I couldn't find the inclusion relation, it seems
> that the B210_impl.cpp is not used at all!It does really confuse me..
> Can the latest UHD support changing the bandwidth of B210? If not ,can I
> modify it?
>
>
> Thank you very very much! :D
>
> Greeting,
> Chuang
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 8
Date: Wed, 5 Mar 2014 15:58:54 -0800
From: Michael West <[email protected]>
To: Ales Povalac <[email protected]>
Cc: usrp-users <[email protected]>
Subject: Re: [USRP-users] RX timeout after longer inactivity
Message-ID:
<cam4xkrqxh5xo-v3akuczebxpky8bebmtus3b9kcuqg0ltvc...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Ales,
Thanks for letting us know. We will try to reproduce the issue and file a
bug if appropriate. I will let you know if we find a workaround or fix.
Best regards,
Michael E. West
Senior Software Design Engineer
Ettus Research
www.ettus.com
On Wed, Mar 5, 2014 at 6:10 AM, Ales Povalac <[email protected]> wrote:
> Dear all,
>
> we have a problem with UHD RX code. If there is a delay between
> get_rx_stream() and issue_stream_cmd() longer than ca. 64 seconds, the
> recv() call always fails with ERROR_CODE_TIMEOUT.
>
> Issue can be reproduced in rx_samples_to_file example by adding a
> delay of >64 seconds before stream command, diff at
> http://pastebin.com/MFDNVyYy . Threshold is near 64 seconds - 60 sec
> always works, 70 sec always fails with "Timeout while streaming".
>
> I am on maint branch of UHD, tested also on 003.005.001 with the same
> result. Any ideas how to fix this issue?
>
> Thanks,
> Ales
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
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Message: 9
Date: Thu, 6 Mar 2014 00:19:53 +0000
From: Juha Vierinen <[email protected]>
To: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] Custom FPGA build for N200R4
Message-ID:
<CAGbkif1UJEep_3AfC2Y0be2RPvM7K6g6eyf2Vw-xtWy=9wd...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Here is an update:
I went from the master branch code back to release
UHD-Mirror-release_003_005_002, which seems to compile just fine with ISE
12.2.
juha
On Wed, Mar 5, 2014 at 9:40 PM, Juha Vierinen <[email protected]> wrote:
> Hi,
>
> I tried doing a custom_dsp_rx module based on the instructions on the git
> source. I also found Tom Hartley's post useful, as the CUSTOM_DEFS caused
> problems with the compiilation environment. I ended up using the "Verilog
> Macros" "LVDS=1|RX_DSP0_MODULE=custom_dsp_rx" approach as suggested in
> Tom's tutorial mail.
>
> However, I still got an error related with missing BUF_SIZE parameter.
> I've pretty much never programmed in verilog, but I am guessing that the
> API for customizing the dsp chain is in a broken state at the moment.
>
> I then went in and pretty much did the changes that I wanted directly in
> ddc_chain.v. I'm trying to compile that right now. We'll see how that goes.
>
> I'm using ISE 12.2, as suggested on the uhd web site.
>
> juha
>
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Message: 10
Date: Thu, 6 Mar 2014 15:21:29 +0800
From: "=?ISO-8859-1?B?NDQyNzc3ODE2?=" <[email protected]>
To: "=?ISO-8859-1?B?VVNSUC11c2Vycw==?=" <[email protected]>
Subject: [USRP-users] UHD & B210 board
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
Another thing has been confusing me , can I use the UHD to write any of the
registers in AD9361?
I found that neither b200_impl.cpp or b200_impl.hpp is included by one
application programme(like rx_samples_to_file.cpp), how can the application
make a device by using the Classes in files which are not included ,such like
b210_impl.hpp?
Thank you all!
Greeting,
Chuang
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Message: 11
Date: Thu, 6 Mar 2014 21:01:15 +1100
From: James Balean <[email protected]>
To: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] B2XX USB 3.0 PCI Express Card
Compatibility/Suggestions
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
Hi Marcus,
Thankyou for the clarification on Marcus M's comments. Hmm - it seems as though
a standard was inadequately standardised if flexibility in implementation can
cause Universal Serial Bus to no longer be universal.
You mentioned that vendor-specific USB classes have 'rough bits' in terms of
device support. As an aside to my original query, can you advise if it might be
worthwhile attempting to add appropriate descriptors such that USRP's
communications conform to a better supported class such as HID?
Do you have any suggestions on 'known-good' USB 3.0 PCI Express cards for the
B2XX in addition to those provided by Marcus L and the benchmark web page?
Particularly, those without additional power requirements?
Thanks again,
James
----------------------------------------
> Date: Wed, 5 Mar 2014 06:45:49 -0500
> From: [email protected]
> To: [email protected]
> Subject: Re: [USRP-users] B2XX USB 3.0 PCI Express Card
> Compatibility/Suggestions
>
> On 03/05/2014 03:47 AM, James Balean wrote:
>>
>>
>> I'm curious as to the cause of the chipset compatibility issues with USRP's.
>> Particularly since you mentioned that some cards are not
>> 'standard-conforming enough'. My assumption was that standards conformance
>> was black and white - if the card and the B2XX device/libusb/drivers/etc
>> conformed to the USB standards, I presumed that they should be able to
>> communicate. Is this not the case? Or does the B2XX/UHD not conform to the
>> USB standards?
>>
>>
>> Thanks again,
>>
>> James
> I worked in the technical-standards community for nearly 15 years. For
> "new" standards (and USB-3.0 is "new") it's not unusual to find that the
> finer
> points of any standard have "rough edges" where implementers disagree
> on the interpretation of parts of the standard, and I believe this to
> be the case here.
>
> Other projects, most notably RASDR, have had issues with USB-3.0
> compatibility, and have had to either dis-recommend a card, or in a
> couple of cases,
> install new *firmware* on the USB-3.0 card to allow it to work properly.
>
> It's unfortunate, but it appears to be the state of the USB-3.0
> ecosystem--when you step outside those devices that fit into a standard
> USB "class" (like storage, network, HID, etc), then you can run into
> "rough bits".
>
>>
>>
>> From: [email protected]
>> To: [email protected]
>> Subject: B2XX USB 3.0 PCI Express Card Compatibility/Suggestions
>> Date: Tue, 4 Mar 2014 23:50:27 +1100
>>
>> USRP Users,
>>
>> I'm hoping for some advice on USB 3.0 PCI Express cards for the B2XX. I am
>> aware that this is a recurring issue in the threads. In my scenario, I am
>> connecting the USRP to a server. The server in question is an HP DL380 G5,
>> with PCIe 1.0 slots. As such, there is no opportunity to attach additional
>> power connectors, which are popular on consumer USB 3.0 cards.
>>
>> It was suggested in previous threads that the compatibility and benchmark
>> matrix on the Ettus website will be updated. Is this likely to be made
>> available in the near future?
>>
>> Does anybody have suggestions for cards worth trying given my constraints
>> above?
>>
>> In particular, has anybody tried HighPoint RocketU cards?
>>
>>
>> Thanks,
>> James
>> _______________________________________________
>> USRP-users mailing list
>> [email protected]
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
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End of USRP-users Digest, Vol 43, Issue 6
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