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Today's Topics:
1. Re: Binary FSK demodulation with symbol timing recovery using
USRP N200 (Mike McLernon)
2. Re: Phase comparator using a N200 (Matt Ettus)
3. UHD/FPGA communication issue (Backen, Staffan)
4. USRP N210 - RAM size (Vinayak Angadi)
5. Looks like the B200 is backordered, how long? (Benito Horta)
6. Re: USRP N210 - RAM size (Marcus M?ller)
7. Re: USRP N210 - RAM size (Marcus M?ller)
8. USRP N210 spurious signal at 900 and 2400 MHz (Usrp IITM)
9. Re: USRP N210 - RAM size (Marcus M?ller)
10. Re: USRP N210 spurious signal at 900 and 2400 MHz (Marcus M?ller)
11. Re: USRP N210 spurious signal at 900 and 2400 MHz (Usrp IITM)
12. FW: USRP N210 spurious signal at 900 and 2400 MHz
(Ralph A. Schmid, dk5ras)
13. Re: USRP N210 spurious signal at 900 and 2400 MHz
(Marcus D. Leech)
14. Re: USRP N210 - RAM size (Ian Buckley)
----------------------------------------------------------------------
Message: 1
Date: Mon, 24 Mar 2014 16:16:41 +0000
From: Mike McLernon <[email protected]>
To: Adeel Malik <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] Binary FSK demodulation with symbol timing
recovery using USRP N200
Message-ID:
<[email protected]>
Content-Type: text/plain; charset="us-ascii"
Hi Adeel,
You will need timing recovery so that the demodulator's integration starts at
the beginning of a symbol and ends at the end of the same symbol. If your
system experiences doppler and timing jitter, a timing recovery subsystem will
be all the more necessary.
The timing recovery should occur before the FSK demodulation.
Hth,
Mike
From: USRP-users [mailto:[email protected]] On Behalf Of Adeel
Malik
Sent: Monday, March 24, 2014 11:19 AM
To: Martin Braun; [email protected]
Subject: [USRP-users] Binary FSK demodulation with symbol timing recovery using
USRP N200
Hi Mr. Braun,
Thanks for your reply. I have already read about the FSK
demodulation functions provided by simulink both for coherent and non-coherent
FSK modulation. However, I am bit uncertain whether I need to include any
Timing / Symbol recovery functionality also at the output stage of FSK
demodulation block (to account for doppler shift in frequencies and timing
jitter when modulating data is about 1 Mbps) ?
If you could suggest how to add a 'symbol timing jitter compensation
functionality' to the output of FSK demodulated data, it would be advantageous.
Regards,
Adeel Malik
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Message: 2
Date: Mon, 24 Mar 2014 09:53:51 -0700
From: Matt Ettus <[email protected]>
To: Juha Vierinen <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] Phase comparator using a N200
Message-ID:
<CAN=1kn8sgHP+o6MGx4Q-XPTAZwv_KskWD+n8T3+=dt9kz6p...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
On Fri, Mar 21, 2014 at 1:49 PM, Juha Vierinen <[email protected]> wrote:
> We first tried the most obvious approach, ie., using the two DDCs with
> with the standard firmware. However, we encountering systematic relative
> phase changes between two channels that were variable over time. We did
> remove the residual frequency error that was there due to the finite length
> tuning word, so that wasn't the cause of the problem. It was as if the two
> NCOs weren't in exactly the same phase at each time step. These phase
> changes are small enough that you won't notice them unless looking at the
> cross channel relative phase difference very carefully (~`100 picoseconds
> peak-to-peak and zero-mean). I never figured out the exact cause of this
> problem, but tuning the DDC to 0 removed the issue. I ended up removing the
> CIC and the half-band filter and just streamed decimated ADC counts on the
> two channels, avoiding nearly all fpga processing. This is a fairly easy
> modification to the UHD Verilog code (this would also be a nice to have
> standard feature for the USRP N200 fpga image).
>
>
We use a 32 bit phase accumulator, but the CORDIC phase rotator only looks
at 24 bits, so the bottom is truncated. This can look like phase jitter,
but it doesn't accumulate. You could get around this by using tuning words
which are zero in all the bottom bits, or just completely remove it as you
have done.
Matt
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Message: 3
Date: Mon, 24 Mar 2014 13:33:19 +0100
From: "Backen, Staffan" <[email protected]>
To: [email protected]
Subject: [USRP-users] UHD/FPGA communication issue
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
Friends -
I have an E110 that does not behave the way I expected it to.
The end goal is to send custom packages from the host to the FPGA, do
some signal processing on the FPGA, and pass some information back. For
now, I have removed all signal processing and set up the FPGA as a "bent
pipe".
I have put a custom module in "custom_dsp_rx.v", and the receive part
works as expected. Further, I have added wires (inside u1plus_core and
down) from the TX side over to the custom_dsp_rx module such that I
should be able to send a custom "command" using usrp_stream->send(),
process data in the fpga and return a custom "message" that is
interpreted on the host side. However, it does not behave as expected.
The "tx_strobe" inside "custom_dsp_rx" goes high when I send a command
for the expected duration (the receive path works fine, so I can for
example count the number of received strobes), but the tx_sample is
always zero when tx_strobe is high.
Is there something I have overlooked here (like a timing issue between
TX strobe/sample), or does this this approach sound reasonable?
If you need any additional information, please let me know.
best,
Staffan
------------------------------
Message: 4
Date: Mon, 24 Mar 2014 18:07:14 +0530
From: Vinayak Angadi <[email protected]>
To: [email protected]
Subject: [USRP-users] USRP N210 - RAM size
Message-ID:
<cajgucfzqs2283eemz5kbsszdq5cqdcyuxjut3pi32fnjvka...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Friends -
I am designing DVB-T2. Which requires large memory to store. When i check
for Spartan-3A DSP only 6% RAM left in Xilinx. I need on board USRP RAM
momory or need to connect to external RAM....
Is USRP N210 has RAM other than FPGA RAM.....?
Regards:
Vinayak
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Message: 5
Date: Mon, 24 Mar 2014 20:03:16 -0400
From: Benito Horta <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] Looks like the B200 is backordered, how long?
Message-ID:
<CAGfuHSpOkORPk-662sTXq8n=+dsaxye+h7rbfvs4xgplhqo...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
14 days so far and still shows awaiting shipping.
I wonder if there is a hardware change being made to the PC board? Or are
these thing in very high demand.
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Message: 6
Date: Tue, 25 Mar 2014 09:20:22 +0100
From: Marcus M?ller <[email protected]>
To: Vinayak Angadi
<[email protected]>,[email protected]
Subject: Re: [USRP-users] USRP N210 - RAM size
Message-ID: <[email protected]>
Content-Type: text/plain; charset=UTF-8
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA512
Hi Vinayak,
There is no external RAM on the N210 as far as I know; you can verify by
considering the schematics on http://files.ettus.com
However, I'm curious: why do you have to decode DVD-t2 on the FPGA? this sounds
like the classical use case for software defined radio on a general purpose
processor like that in your PC...
Greetings,
Marcus
On March 24, 2014 1:37:14 PM CET, Vinayak Angadi <[email protected]>
wrote:
>Friends -
>
>I am designing DVB-T2. Which requires large memory to store. When i
>check
>for Spartan-3A DSP only 6% RAM left in Xilinx. I need on board USRP RAM
>momory or need to connect to external RAM....
>
>Is USRP N210 has RAM other than FPGA RAM.....?
>
>
>
>Regards:
>Vinayak
>
>
>------------------------------------------------------------------------
>
>_______________________________________________
>USRP-users mailing list
>[email protected]
>http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
- --
Sent from my Android device with K-9 Mail. Please excuse my brevity.
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Message: 7
Date: Tue, 25 Mar 2014 10:26:40 +0100
From: Marcus M?ller <[email protected]>
To: Vinayak Angadi
<[email protected]>,[email protected]
Subject: Re: [USRP-users] USRP N210 - RAM size
Message-ID: <[email protected]>
Content-Type: text/plain; charset=UTF-8
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA512
This sounds like class / lab assignment. If that's the case, aim for something
much simpler than decoding a digital television broadcast for starters.
Also, you misunderstood: " general purpose " refers to the kind of processor
you run your decoder on, not to the purpose of DVB-t2.
Greetings,
Marcus
On March 25, 2014 9:55:11 AM CET, Vinayak Angadi <[email protected]>
wrote:
>Thank you for replay....
>
>Need to design decoder using Verilog or VHDL.... U can use DVB-T2 for
>any
>purpose.....
>
>
>On 25 March 2014 13:50, Marcus M?ller <[email protected]> wrote:
>
>> -----BEGIN PGP SIGNED MESSAGE-----
>> Hash: SHA512
>>
>> Hi Vinayak,
>>
>> There is no external RAM on the N210 as far as I know; you can verify
>by
>> considering the schematics on http://files.ettus.com
>>
>> However, I'm curious: why do you have to decode DVD-t2 on the FPGA?
>this
>> sounds like the classical use case for software defined radio on a
>general
>> purpose processor like that in your PC...
>>
>> Greetings,
>> Marcus
>>
>> On March 24, 2014 1:37:14 PM CET, Vinayak Angadi
><[email protected]>
>> wrote:
>> >Friends -
>> >
>> >I am designing DVB-T2. Which requires large memory to store. When i
>> >check
>> >for Spartan-3A DSP only 6% RAM left in Xilinx. I need on board USRP
>RAM
>> >momory or need to connect to external RAM....
>> >
>> >Is USRP N210 has RAM other than FPGA RAM.....?
>> >
>> >
>> >
>> >Regards:
>> >Vinayak
>> >
>> >
>>
>>------------------------------------------------------------------------
>> >
>> >_______________________________________________
>> >USRP-users mailing list
>> >[email protected]
>> >http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>> - --
>> Sent from my Android device with K-9 Mail. Please excuse my brevity.
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>>
>>
- --
Sent from my Android device with K-9 Mail. Please excuse my brevity.
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------------------------------
Message: 8
Date: Tue, 25 Mar 2014 15:19:50 +0530
From: Usrp IITM <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] USRP N210 spurious signal at 900 and 2400 MHz
Message-ID:
<CAPkh=_8vbgqyea8xbmlzw6+yopr5f+woyh+jv1921tnq+qh...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi,
We were performing a very simple experiment where we produced a signal
using an RF function generator, and connected it to the USRP N210 (using
an SBX daughterboard) an SMA cable.
In the experiment shown in the screenshot (attached), we transmitted a sine
wave at 2.405GHz, -40dBm, and we were looking at the spectrum using
uhd_fft, with a centre frequency of 2.401GHz.
Two questions:
1. We get a very significant spike at 2.4GHz. This seems to be too large
for it to be coming from some Wifi access points, especially since we
aren't using any antenna. *This spike is observed even when we remove
the signal from the function generator*. Could this be something caused
by the daughterboard?
2. Assuming that uhd_fft downconverts the signal using the specified
frequency (2.401GHz), should we not also expect to see a large spike at
2.401 - (2.405 - 2.401) = 2.397GHz?
Regards,
Praveen
(USRP Users IITM)
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Message: 9
Date: Tue, 25 Mar 2014 11:41:14 +0100
From: Marcus M?ller <[email protected]>
To: Vinayak Angadi
<[email protected]>,[email protected]
Subject: Re: [USRP-users] USRP N210 - RAM size
Message-ID: <[email protected]>
Content-Type: text/plain; charset=UTF-8
-----BEGIN PGP SIGNED MESSAGE-----
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Well, in that case, N210 is definitely not the platform you should be working
on.
The USRP line of devices is intended to be used as software radio front ends.
While this might mean that you have to do some processing in the FPGA for
example to react to channel occupancy without the latency added by transferring
samples to the host, the idea is to do your signal processing on the host (PC)
and use the USRP basically as a kind of high quality upcoming complex baseband
soundcard.
Wanting to do the complete DVB-t2 standard in a USRP is not what the N210 was
meant to do. The FPGA is too small, it is hardly possible to attach external
ram fast enough, and honestly it seems like a bad design choice.
Do the signal generation on a PC, and teacher the samples to the N210, would be
my advice. Talk to your advisor.
If you absolutely must do complex calculation on an FPGA, take a look at the
Ettus x300 series. They have larger FPGAs.
Greetings,
Marcus
On March 25, 2014 10:36:51 AM CET, Vinayak Angadi <[email protected]>
wrote:
>Yes, coding for final year project(Intern). I am designing only for
>encoder(Tx side).....
>
>
>On 25 March 2014 14:56, Marcus M?ller <[email protected]> wrote:
>
>> -----BEGIN PGP SIGNED MESSAGE-----
>> Hash: SHA512
>>
>> This sounds like class / lab assignment. If that's the case, aim for
>> something much simpler than decoding a digital television broadcast
>for
>> starters.
>>
>> Also, you misunderstood: " general purpose " refers to the kind of
>> processor you run your decoder on, not to the purpose of DVB-t2.
>>
>> Greetings,
>> Marcus
>>
>> On March 25, 2014 9:55:11 AM CET, Vinayak Angadi
><[email protected]>
>> wrote:
>> >Thank you for replay....
>> >
>> >Need to design decoder using Verilog or VHDL.... U can use DVB-T2
>for
>> >any
>> >purpose.....
>> >
>> >
>> >On 25 March 2014 13:50, Marcus M?ller <[email protected]> wrote:
>> >
>> >> -----BEGIN PGP SIGNED MESSAGE-----
>> >> Hash: SHA512
>> >>
>> >> Hi Vinayak,
>> >>
>> >> There is no external RAM on the N210 as far as I know; you can
>verify
>> >by
>> >> considering the schematics on http://files.ettus.com
>> >>
>> >> However, I'm curious: why do you have to decode DVD-t2 on the
>FPGA?
>> >this
>> >> sounds like the classical use case for software defined radio on a
>> >general
>> >> purpose processor like that in your PC...
>> >>
>> >> Greetings,
>> >> Marcus
>> >>
>> >> On March 24, 2014 1:37:14 PM CET, Vinayak Angadi
>> ><[email protected]>
>> >> wrote:
>> >> >Friends -
>> >> >
>> >> >I am designing DVB-T2. Which requires large memory to store. When
>i
>> >> >check
>> >> >for Spartan-3A DSP only 6% RAM left in Xilinx. I need on board
>USRP
>> >RAM
>> >> >momory or need to connect to external RAM....
>> >> >
>> >> >Is USRP N210 has RAM other than FPGA RAM.....?
>> >> >
>> >> >
>> >> >
>> >> >Regards:
>> >> >Vinayak
>> >> >
>> >> >
>> >>
>>
>>>------------------------------------------------------------------------
>> >> >
>> >> >_______________________________________________
>> >> >USRP-users mailing list
>> >> >[email protected]
>> >>
>>http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>> >>
>> >> - --
>> >> Sent from my Android device with K-9 Mail. Please excuse my
>brevity.
>> >> -----BEGIN PGP SIGNATURE-----
>> >> Version: APG v1.1.1
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>> >>
>> >>
>>
>> - --
>> Sent from my Android device with K-9 Mail. Please excuse my brevity.
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>> Version: APG v1.1.1
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>>
>>
- --
Sent from my Android device with K-9 Mail. Please excuse my brevity.
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------------------------------
Message: 10
Date: Tue, 25 Mar 2014 11:46:14 +0100
From: Marcus M?ller <[email protected]>
To: Usrp IITM <[email protected]>, "[email protected]"
<[email protected]>
Subject: Re: [USRP-users] USRP N210 spurious signal at 900 and 2400
MHz
Message-ID: <[email protected]>
Content-Type: text/plain; charset=UTF-8
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA512
Two short answers:
1.
This might be local oscillator leakage.
2. Not uhd_fft does the downconversion but the USRP.
This is complex baseband of the specified sample rate as bandwidth. Aliasing
will not occur since the USRP does it right and has a band pass in front of the
mixer as well as low passes in the digital downconversion chain.
Greetings,
Marcus
On March 25, 2014 10:49:50 AM CET, Usrp IITM <[email protected]> wrote:
>Hi,
>
>We were performing a very simple experiment where we produced a signal
>using an RF function generator, and connected it to the USRP N210
>(using
>an SBX daughterboard) an SMA cable.
>
>In the experiment shown in the screenshot (attached), we transmitted a
>sine
>wave at 2.405GHz, -40dBm, and we were looking at the spectrum using
>uhd_fft, with a centre frequency of 2.401GHz.
>
>Two questions:
>
>1. We get a very significant spike at 2.4GHz. This seems to be too
>large
> for it to be coming from some Wifi access points, especially since we
> aren't using any antenna. *This spike is observed even when we remove
>the signal from the function generator*. Could this be something caused
> by the daughterboard?
> 2. Assuming that uhd_fft downconverts the signal using the specified
>frequency (2.401GHz), should we not also expect to see a large spike at
> 2.401 - (2.405 - 2.401) = 2.397GHz?
>
>Regards,
>Praveen
>(USRP Users IITM)
>
>
>------------------------------------------------------------------------
>
>_______________________________________________
>USRP-users mailing list
>[email protected]
>http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
- --
Sent from my Android device with K-9 Mail. Please excuse my brevity.
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------------------------------
Message: 11
Date: Tue, 25 Mar 2014 17:47:28 +0530
From: Usrp IITM <[email protected]>
To: Marcus M?ller <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] USRP N210 spurious signal at 900 and 2400
MHz
Message-ID:
<CAPkh=_-4my9=XciWgBaSUp2a6+OO34c=oj0natwjdvn9vmt...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi,
I think it is unlikely to be LO leakage. The 2.4GHz spike shows up even
when we use other center frequencies (2.402GHz, etc.) Moreover, the spike
is really large. I know that the readings are not absolute, but we do have
the actual transmitted signal (2.405) for reference - that one is -40dBm,
so the one at 2.4GHz is around -65 to -70dBm, right? Also there is a small
spike at 2.401, so I guess that corresponds to the LO leakage.
And for the second question, are these filters in the quadrature
demodulator (i.e. in the ADL5380)?
Regards,
Praveen
(USRP users IITM)
On Tue, Mar 25, 2014 at 4:16 PM, Marcus M?ller <[email protected]> wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA512
>
> Two short answers:
> 1.
> This might be local oscillator leakage.
>
> 2. Not uhd_fft does the downconversion but the USRP.
> This is complex baseband of the specified sample rate as bandwidth.
> Aliasing will not occur since the USRP does it right and has a band pass in
> front of the mixer as well as low passes in the digital downconversion
> chain.
>
> Greetings,
> Marcus
>
> On March 25, 2014 10:49:50 AM CET, Usrp IITM <[email protected]>
> wrote:
> >Hi,
> >
> >We were performing a very simple experiment where we produced a signal
> >using an RF function generator, and connected it to the USRP N210
> >(using
> >an SBX daughterboard) an SMA cable.
> >
> >In the experiment shown in the screenshot (attached), we transmitted a
> >sine
> >wave at 2.405GHz, -40dBm, and we were looking at the spectrum using
> >uhd_fft, with a centre frequency of 2.401GHz.
> >
> >Two questions:
> >
> >1. We get a very significant spike at 2.4GHz. This seems to be too
> >large
> > for it to be coming from some Wifi access points, especially since we
> > aren't using any antenna. *This spike is observed even when we remove
> >the signal from the function generator*. Could this be something caused
> > by the daughterboard?
> > 2. Assuming that uhd_fft downconverts the signal using the specified
> >frequency (2.401GHz), should we not also expect to see a large spike at
> > 2.401 - (2.405 - 2.401) = 2.397GHz?
> >
> >Regards,
> >Praveen
> >(USRP Users IITM)
> >
> >
> >------------------------------------------------------------------------
> >
> >_______________________________________________
> >USRP-users mailing list
> >[email protected]
> >http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
> - --
> Sent from my Android device with K-9 Mail. Please excuse my brevity.
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>
>
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Message: 12
Date: Tue, 25 Mar 2014 13:41:26 +0100
From: "Ralph A. Schmid, dk5ras" <[email protected]>
To: "'USRP List'" <[email protected]>
Subject: [USRP-users] FW: USRP N210 spurious signal at 900 and 2400
MHz
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
My USRP1 with WBX produces some spikes that clearly are multiples of the
master clock. They also can be shown with an independent spectrum
analyzer. However I do not have them in such a strength at 2.smth GHz, they
get weaker and weaker above 1 GHz...
Ralph.
> > -----Original Message-----
> > From: USRP-users [mailto:[email protected]] On Behalf
> > Of Marcus M?ller
> > Sent: Tuesday, March 25, 2014 11:46 AM
> > To: Usrp IITM; [email protected]
> > Subject: Re: [USRP-users] USRP N210 spurious signal at 900 and 2400
> > MHz
> >
> > * PGP Signed by an unverified key: 25.03.2014 at 11:46:13
> >
> > Two short answers:
> > 1.
> > This might be local oscillator leakage.
> >
> > 2. Not uhd_fft does the downconversion but the USRP.
> > This is complex baseband of the specified sample rate as bandwidth.
> > Aliasing will not occur since the USRP does it right and has a band
> > pass in front of the mixer as well as low passes in the digital
> downconversion chain.
> >
> > Greetings,
> > Marcus
> >
> > On March 25, 2014 10:49:50 AM CET, Usrp IITM
> > <[email protected]>
> > wrote:
> > >Hi,
> > >
> > >We were performing a very simple experiment where we produced a
> > >signal using an RF function generator, and connected it to the USRP
> > >N210 (using an SBX daughterboard) an SMA cable.
> > >
> > >In the experiment shown in the screenshot (attached), we transmitted
> > >a sine wave at 2.405GHz, -40dBm, and we were looking at the spectrum
> > >using uhd_fft, with a centre frequency of 2.401GHz.
> > >
> > >Two questions:
> > >
> > >1. We get a very significant spike at 2.4GHz. This seems to be too
> > >large
> > > for it to be coming from some Wifi access points, especially since
> > >we
> > > aren't using any antenna. *This spike is observed even when we
> > >remove the signal from the function generator*. Could this be something
> caused
> > > by the daughterboard?
> > > 2. Assuming that uhd_fft downconverts the signal using the
> > >specified frequency (2.401GHz), should we not also expect to see a
large
> spike at
> > > 2.401 - (2.405 - 2.401) = 2.397GHz?
> > >
> > >Regards,
> > >Praveen
> > >(USRP Users IITM)
> > >
> > >
> > >---------------------------------------------------------------------
> > >--
> > >-
> > >
> > >_______________________________________________
> > >USRP-users mailing list
> > >[email protected]
> > >http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> >
> > --
> > Sent from my Android device with K-9 Mail. Please excuse my brevity.
> >
> > * Marcus M?ller <[email protected]>
> > * 0xF2CE51ED:0xE926F7E8 - Unverified(L)
> >
> >
> > _______________________________________________
> > USRP-users mailing list
> > [email protected]
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 13
Date: Tue, 25 Mar 2014 09:13:07 -0400
From: "Marcus D. Leech" <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] USRP N210 spurious signal at 900 and 2400
MHz
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
On 03/25/2014 08:17 AM, Usrp IITM wrote:
> Hi,
>
> I think it is unlikely to be LO leakage. The 2.4GHz spike shows up
> even when we use other center frequencies (2.402GHz, etc.) Moreover,
> the spike is really large. I know that the readings are not absolute,
> but we do have the actual transmitted signal (2.405) for reference -
> that one is -40dBm, so the one at 2.4GHz is around -65 to -70dBm,
> right? Also there is a small spike at 2.401, so I guess that
> corresponds to the LO leakage.
>
> And for the second question, are these filters in the quadrature
> demodulator (i.e. in the ADL5380)?
>
> Regards,
> Praveen
> (USRP users IITM)
If you terminate the input with a resistive terminator, and tune to
2.401GHz, do you still see a spike at 2.400GHz? If so, my guess is that
it's
a harmonic (24th) of the 100Mhz master clock.
--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
------------------------------
Message: 14
Date: Tue, 25 Mar 2014 08:23:58 -0700
From: Ian Buckley <[email protected]>
To: Vinayak Angadi <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] USRP N210 - RAM size
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
Vinayak,
The default FPGA design in the N210 is designed to offer as many features as
possible for the majority of users, and thus it uses a considerable amount of
the FPGA resources. Any particular user generally only uses a subset of those
features on any one project. In your case, if you are designing a DVB-T2
modulator in H/W then for example you do not need either of the receive (RX)
DSP chains, and thus you can free up the logic used by those resources. In the
default design, the external 1M Byte SRAM provided on N210 is used exclusively
for TX buffering of sample data. You are free to use that for other purposes
provided you provide an alternate and suitable buffer for data that is of
appropriate size to deal with your incoming data rate and the upstream provider.
-Ian
On Mar 24, 2014, at 5:37 AM, Vinayak Angadi <[email protected]> wrote:
>
> Friends -
>
> I am designing DVB-T2. Which requires large memory to store. When i check for
> Spartan-3A DSP only 6% RAM left in Xilinx. I need on board USRP RAM momory or
> need to connect to external RAM....
>
> Is USRP N210 has RAM other than FPGA RAM.....?
>
>
>
> Regards:
> Vinayak
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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