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Today's Topics:
1. Programmatic detection of incompatible UHD Host Code with
USRP N210 FPGA/Firmware (Perelman Nathan (Nathan))
2. Re: Error when trying to stream from Rx0 and Rx1 on a B210
board. ([email protected])
3. Re: Error when trying to stream from Rx0 and Rx1 on a B210
board. (Marcus D. Leech)
4. Re: Full bandwidth streaming from X300 to disk (Matt Ettus)
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Message: 1
Date: Fri, 4 Apr 2014 15:27:19 -0400
From: "Perelman Nathan (Nathan)" <[email protected]>
To: <[email protected]>
Subject: [USRP-users] Programmatic detection of incompatible UHD Host
Code with USRP N210 FPGA/Firmware
Message-ID:
<3862c5643b15b6468269546753eb2a9209fca...@bltsxvs01.govsolutions.com>
Content-Type: text/plain; charset="us-ascii"
Is there a programmatic way of detecting when the UHD Host Code is
incompatible with the USRP2/N210/N200 FPGA/firmware load? I'd like to be
able to notify users of my application that they need to upgrade the
FPGA/firmware load on their USRP. I see
(https://github.com/EttusResearch/uhd/blob/master/host/lib/usrp/usrp2/us
rp2_impl.cpp#L394 ) that an exception is thrown, however it is just of
the generic uhd::runtime_error type and I'd like to avoid parsing the
string included in the exception if possible. Thanks.
-Nathan Perelman
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Message: 2
Date: Fri, 4 Apr 2014 12:34:05 -0700 (PDT)
From: "[email protected]" <[email protected]>
To: "[email protected]" <[email protected]>
Cc: "[email protected]" <[email protected]>, david
seebran <[email protected]>
Subject: Re: [USRP-users] Error when trying to stream from Rx0 and Rx1
on a B210 board.
Message-ID:
<[email protected]>
Content-Type: text/plain; charset="us-ascii"
I am trying to simultaneously stream from both channels (Rx0 and Rx1) on a B210
board. However, I am
getting the following error:
UHD Error: The receive packet handler failed to time-align packets. nnnn
received packets were processed by the handler. However, a timestamp match
could not be determined.
David Seebran
[email protected]
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Message: 3
Date: Fri, 04 Apr 2014 15:55:23 -0400
From: "Marcus D. Leech" <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] Error when trying to stream from Rx0 and Rx1
on a B210 board.
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"; Format="flowed"
On 04/04/2014 03:34 PM, [email protected] wrote:
> I am trying to simultaneously stream from both channels (Rx0 and Rx1) on a
> B210 board. However, I am
> getting the following error:
>
> UHD Error:
> The receive packet handler failed to time-align packets.
> nnnn received packets were processed by the handler.
> However, a timestamp match could not be determined.
>
>
>
>
> David Seebran
> [email protected]
What version of UHD are you using, and how are you setting up your
streamers? Are they both part of the same multi_usrp object, or
different objects? How are you specifying the subdevs?
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Message: 4
Date: Fri, 4 Apr 2014 16:44:55 -0700
From: Matt Ettus <[email protected]>
To: Perper <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] Full bandwidth streaming from X300 to disk
Message-ID:
<CAN=1kn9pZaxy=byonn+1fgfidox4+bqq+shob-gs+upsp0f...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
On the X300 and X310, you can select the master clock rate that you want,
and the ADC and DAC are clocked at that rate. 200 MHz is the default rate,
but 184.32 MHz (ideal for LTE and 3G) is also commonly used. Not all rates
have equally good phase noise and jitter, but most multiples of 4 MHz, 5
MHz, 3.84 MHz, or 4.8 MHz will be very good. If you have questions about a
specific rate, just ask and we'll tell you if it is a good one.
Matt
On Fri, Apr 4, 2014 at 4:26 AM, Perper <[email protected]> wrote:
> W dniu 27.03.2014 20:26, Marcus D. Leech pisze:
> >> My question was not about downsampling/ddc. I understand how that
> works.
> >> My question was about going from 200 MHz down to 150 MHz, which would
> >> presumably require an actual change to the A/D clock.
> > Ah. Presumably because you're only *really* interested in 75Msps
> sample-rate--100Msps too much, 50Msps too little?
> >
> > It has configurable clocking, so, yeah, you could likely change it to
> 150MHz master-clock rate if you
> > wanted.
> >
> >
>
> Hi Marcus,
>
> What do you mean by saying there is "configurable clocking" in USRP
> X300? You mean that you can change clock that enters ADC?
> The datasheet of X300 says something about "Flexible clocking
> architecture" but I couldn't find info what exactly is meant by this
> statement.
>
> --
> Best Regards,
> Piotr Krysik
>
> >> John
> >>
> >>> -----Original Message-----
> >>> From: USRP-users [mailto:[email protected]] On
> Behalf Of
> >>> Marcus M?ller
> >>> Sent: Thursday, March 27, 2014 3:16 PM
> >>> To: [email protected]
> >>> Subject: Re: [USRP-users] Full bandwidth streaming from X300 to disk
> >>>
> > Yes, the USRP architecture allows you to downsample the ADC to the
> desired
> > sampling rate, doing all the necessary filtering in-FPGA.
> > So you specify 10Msps, you get an alias-free 10Msps :)
> >
> > Greetings,
> > Marcus
> >
> > On 27.03.2014 20:13, Mann, John P. - 1003 - MITLL wrote:
> > >>>> Marcus D. Leech <[email protected]> wrote:
> > >>>>>> The analog daughtercards for X3xx series have 120Mhz of
> > >>>>>> *complex* analog
> > >>>> bandwidth,
> > >>>>>> which is sampled by a 200Msps complex (I and Q) ADC. No violation
> > >>>>>> of
> > >>>> Nyquist involved at all.
> > >>>>
> > >>>> I was not aware that the 200 MHz ADC spec was already a quadrature
> > >>>> rate. Thank you for clearing that up! So there is actually a ton of
> > >>>> extra headroom to handle 120 MHz bandwidth coming out of the
> daughter
> > >>>> boards... Can I easily lower the sample rate down to something like
> > >>>> 150 MHz to save disk space?
> > >>>>
> > >>>> John Mann
> > >>>>
> > >>>>
> > >>>>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
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