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Today's Topics:
1. USRP N210 maximum and minimum Tx/Rx Power (Touseef Ali)
2. Re: USRP N210 maximum and minimum Tx/Rx Power (Marcus D. Leech)
3. full-scale range on B210 (Sivan Toledo)
4. Re: Achieving higher sampling rates with the N210 for
multi-constellation GNSS record-playback (Adrian Martinez Gomez)
5. Re: Programmatic detection of incompatible UHD Host Code with
USRP N210 FPGA/Firmware (Martin Braun)
6. USRP n210 sram type (BHASKAR BANERJEE)
7. Re: USRP n210 sram type (Marcus M?ller)
8. Re: Sweeping the center frequency in USRP over a wide band
(Mike Jameson)
9. Re: full-scale range on B210 (Mike Jameson)
10. Re: full-scale range on B210 (Mike Jameson)
11. Re: full-scale range on B210 (Mike Jameson)
12. N200 or N210 with baseband input (Dan Sego)
13. Re: N200 or N210 with baseband input (Mike Jameson)
14. Re: N200 or N210 with baseband input (Marcus M?ller)
15. Re: N200 or N210 with baseband input (Ralph A. Schmid, dk5ras)
16. Re: N200 or N210 with baseband input (Ralph A. Schmid, dk5ras)
17. Re: N200 or N210 with baseband input (Mike Jameson)
18. Re: full-scale range on B210 (Sivan Toledo)
19. Re: Achieving higher sampling rates with the N210 for
multi-constellation GNSS record-playback (Ian Buckley)
20. Re: full-scale range on B210 (Ian Buckley)
----------------------------------------------------------------------
Message: 1
Date: Sun, 6 Apr 2014 21:13:47 +0500
From: Touseef Ali <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] USRP N210 maximum and minimum Tx/Rx Power
Message-ID: <[email protected]>
Content-Type: text/plain; charset=us-ascii
Hi,
What is the maximum and minimum power that a USRP N210, fitted with CBX
daughterboard, can transmit and receive without damaging the kit.?
And what is the maximum and minimum power that a USRP N210, fitted with LFRX
daughterboard, can receive without damaging the kit?
Regards
Touseef Ali
------------------------------
Message: 2
Date: Sun, 06 Apr 2014 12:39:05 -0400
From: "Marcus D. Leech" <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] USRP N210 maximum and minimum Tx/Rx Power
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
On 04/06/2014 12:13 PM, Touseef Ali wrote:
> Hi,
> What is the maximum and minimum power that a USRP N210, fitted with CBX
> daughterboard, can transmit and receive without damaging the kit.?
> And what is the maximum and minimum power that a USRP N210, fitted with LFRX
> daughterboard, can receive without damaging the kit?
>
> Regards
> Touseef Ali
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
The CBX outputs a maximum of about +20dBm, depending on frequency, it
has ~30dB of gain-control range, so minimum output power is
somewhere around -10dBm, again depending on frequency. The maximum
recommended input power is around -15dBm for the CBX, the
MDS for a narrowband signal should be somewhere south of -100dBm.
The LFRX has no gain, so max input power is about +10dBm, and MDS is
probably somewhere around -75dBm, possibly lower.
------------------------------
Message: 3
Date: Mon, 7 Apr 2014 10:29:00 +0300
From: Sivan Toledo <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] full-scale range on B210
Message-ID:
<CAOL_ruFQfAFT7hex+47J04V8gJp0xzZC_GkKbAJPG=hjbvy...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi,
I run the same UHD code on both the N200 and the B210. On the N200, full
scale receive output (ADC is saturated) is 32767. On the B210, full scale
appears to be 9930. This is at both 4MHz and 8MHz sample rate. The UHD code
is identical.
Is the full-scale range of the B210 indeed 9930? If not, is there a likely
reason that I don't see higher values?
Thanks, Sivan
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Message: 4
Date: Mon, 7 Apr 2014 10:27:20 +0200
From: Adrian Martinez Gomez <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] Achieving higher sampling rates with the
N210 for multi-constellation GNSS record-playback
Message-ID:
<cabefxyceq0ergay4wq3_vzg+lnigkhdv9elqtapcbmo0g1e...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hello all,
although I know this is probably no USRP specific question, but rather a
Xilinx one, I would want to know the opinion of the ones of you who have
worked with the FPGA code.
What I am trying to do is just to generate the bin file for the FPGA for
the USRP N210 myself, using the ISE Suite Edition (12.2 version; with 30
day trial license).
I followed the instruction on the README.txt on the fpga folder of
https://github.com/EttusResearch/uhd/tree/master/fpga
When running "make -f Makefile.N210R4 bin" I get the following in the
build.log file, and an empty .bin build:
*Mapping completed. *
*See MAP report file u2plus_map.mrp for details.*
*/opt/Xilinx/12.2/ISE_DS/ISE/bin/lin64/unwrapped/ma**p: symbol lookup
error: /opt/Xilinx/12.2/ISE_DS/ISE//lib/lin64/libXst_Core**.so: undefined
symbol: _ZN5antlr6BitSetD1Ev*
* Process "Map" failed*
Did someone have the same issue? Some ideas on what might have gone wrong?
The FPGA code is unmodified, I only wanted to be able to generate the FPGA
image myself (for future modifications).
Thanks in advance!
P.S. attached you will find my build.log as well as my u2plus_map.mrp (in
case it helps)
build.log<https://docs.google.com/file/d/0B1MBvlNk1q2sbkRHaWhkZ1lYRnp2bXgzY2F1S212TjBkby0w/edit?usp=drive_web>
u2plus_map.mrp<https://docs.google.com/file/d/0B1MBvlNk1q2sdWNoVFBYdWRlWlFMT1M5aTFseW9sTnkyQmhR/edit?usp=drive_web>
On Thu, Apr 3, 2014 at 4:42 PM, Adrian Martinez Gomez <
[email protected]> wrote:
> At the end another NIC (already on the PC, just another port) worked just
> fine.
>
> @Marcus. For the time being I will stick with trying to do the reduction
> on the FPGA. The network bandwidth would be also a motivation for doing it
> this way.
>
>
> On Thu, Apr 3, 2014 at 2:14 PM, Martin Braun <[email protected]>wrote:
>
>> On 04/02/2014 03:20 PM, Adrian Martinez Gomez wrote:
>> > Quick update:
>> > I achieved the 25Msps and sc16 as well as 50Msps and sc8 with some NIC
>> > work. Now both rx and tx work fine.
>>
>> Hi Adrian,
>>
>> what did you do? Did you try another NIC, or do some configuration?
>>
>> Martin
>>
>>
>> _______________________________________________
>> USRP-users mailing list
>> [email protected]
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>
>
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Message: 5
Date: Mon, 07 Apr 2014 11:05:22 +0200
From: Martin Braun <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] Programmatic detection of incompatible UHD
Host Code with USRP N210 FPGA/Firmware
Message-ID: <[email protected]>
Content-Type: text/plain; charset=windows-1252
On 04/04/2014 09:27 PM, Perelman Nathan (Nathan) wrote:
> Is there a programmatic way of detecting when the UHD Host Code is
> incompatible with the USRP2/N210/N200 FPGA/firmware load? I?d like to be
> able to notify users of my application that they need to upgrade the
> FPGA/firmware load on their USRP. I see
> (https://github.com/EttusResearch/uhd/blob/master/host/lib/usrp/usrp2/usrp2_impl.cpp#L394
> ) that an exception is thrown, however it is just of the generic
> uhd::runtime_error type and I?d like to avoid parsing the string
> included in the exception if possible. Thanks.
Nathan,
the exception is thrown inside the USRP2 constructor, so you can't
create a USRP first, and then check the fw version later if there was a
version mismatch.
Unless you want to write a mini-usrp2 controller class that replicates
the code inside usrp2_impl that sets up the motherboard controller
interface, it's probably much easier to catch the exception and parse
the string -- it's a static message, and you can just search of a unique
substring, like "Expected FPGA compatibility number".
And even if you don't catch it, the user will see a descriptive error
message.
Martin
------------------------------
Message: 6
Date: Mon, 7 Apr 2014 14:50:35 +0530
From: BHASKAR BANERJEE <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] USRP n210 sram type
Message-ID:
<CAB=Xdsm04Yv5aRYs+qjdPM=yyj21mmf_gvmagraodm9pxv3...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi
I wanted to know the sram in USRP n210 is a single data rate ram or a
double data data rate ram.
Thanks
Bhaskar Banerjee
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Message: 7
Date: Mon, 07 Apr 2014 11:49:48 +0200
From: Marcus M?ller <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] USRP n210 sram type
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1
-----BEGIN PGP SIGNED MESSAGE-----
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Hi Bhaskar Banerjee,
I'm not quite sure what you're addressing:
- - The RAM on the FPGA in the form of so-called block RAM is SRAM --
the term double data rate does not usually apply to that.
- - The Cypress RAM on board is also SRAM; double/single data rate
doesn't apply here, either.
Technically, SRAM outputs a single data word per clock.
Since I don't think I've answered your *original* question, could you
explain why you were asking for DDR/SDR RAM?
Greetings,
Marcus
On 07.04.2014 11:20, BHASKAR BANERJEE wrote:
> Hi
>
> I wanted to know the sram in USRP n210 is a single data rate ram or
> a double data data rate ram.
>
> Thanks Bhaskar Banerjee
>
>
>
> _______________________________________________ USRP-users mailing
> list [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
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------------------------------
Message: 8
Date: Mon, 7 Apr 2014 12:25:09 +0100
From: Mike Jameson <[email protected]>
To: Touseef Ali <[email protected]>,
"[email protected]" <[email protected]>
Subject: Re: [USRP-users] Sweeping the center frequency in USRP over a
wide band
Message-ID:
<cajcjmitxs1kzyiu+ytxk93fvsg2kw7mvw-htdqw++dnjhfk...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Glad to hear it's working for you. To change the delay before each center
freq change you will need to change the 'poll rate' setting in the
'function probe' block called func_center_freq. It is currently set to 1
Hz (1 hop per second). Instead of trying to edit the raw .py file, I'd
recommend using 'gnuradio-companion' to load the uhd_tx_sweep.grc file and
then double click on the 'function probe' to change it. Be aware that if
you have made any modifications to the raw .py file, then any changes will
be overwritten when you execute the flowgraph from the GRC GUI.
Mike
--
Mike Jameson M0MIK BSc MIET
Email: [email protected]
Web: http://scanoo.com
On Mon, Apr 7, 2014 at 7:44 AM, Touseef Ali <[email protected]>wrote:
> Hi Mike!
> I tried your code and it is working. But how can I determine the sweep
> time and change it?
>
> Best Regards
> Touseef Ali
> On Apr 3, 2014, at 5:14 PM, Mike Jameson <[email protected]> wrote:
>
> Touseef,
>
> See attached for something I've just put together which sweeps the
> transmit freq from 'center_freq_min' to 'center_freq_max' in 6.25e3 steps.
> It is currently configured for a usrp2 with external clock source so you
> will need to change this to your hardware accordingly.
>
> Mike
>
> --
> Mike Jameson M0MIK BSc MIET
> Email: [email protected]
> Web: http://scanoo.com
>
>
> On Thu, Mar 27, 2014 at 5:32 PM, Ben Hilburn <[email protected]>wrote:
>
>> Hi Touseef -
>>
>> You will need to write a program to do this, or create a flowgraph using
>> GNURadio. None of the built-in UHD example applications provide the
>> functionality you are looking for.
>>
>> You may consider starting with the `uhd_fft` program distributed with
>> GNURadio, and modifying the code from there.
>>
>> Cheers,
>> Ben
>>
>>
>> On Mon, Mar 24, 2014 at 8:21 AM, Touseef Ali <[email protected]>wrote:
>>
>>> Hi!
>>> I want to sweep the center frequency over a bandwidth of 1.25 GHz. I
>>> tried using the 'sweep' option in 'uhd_siggen_gui' but it does not move the
>>> center frequency and the bandwidth over which it sweeps the signal is
>>> hardly 100 MHz. I want to sweep the center frequency just like the slider
>>> does in 'uhd_siggen_gui' but I want do it automatically and in steps (just
>>> like a digital signal generator).
>>>
>>> Regards
>>> Touseef Ali
>>>
>>> _______________________________________________
>>> USRP-users mailing list
>>> [email protected]
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>>
>>
>> _______________________________________________
>> USRP-users mailing list
>> [email protected]
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>>
> <uhd_tx_sweep.grc>
>
> <uhd_tx_sweep.grc.png>
>
> <uhd_tx_sweep.py>
>
>
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Message: 9
Date: Mon, 7 Apr 2014 13:00:09 +0100
From: Mike Jameson <[email protected]>
To: Sivan Toledo <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] full-scale range on B210
Message-ID:
<CAJcjmiR8YYTvXAVYB=ra7t9odmxq8xc-uvu6d04wzuittrf...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Sivan,
The ADC in a N200 is 14-bit (2**14 = 16384) and the ADC in a B210 is 12-bit
(2**12 = 4096).
If you multiply the number of quantisation points by two, to include
negative values (in the time domain), it looks close to what you are seeing.
Mike
--
Mike Jameson M0MIK BSc MIET
Email: [email protected]
Web: http://scanoo.com
On Mon, Apr 7, 2014 at 8:29 AM, Sivan Toledo <[email protected]> wrote:
> Hi,
>
> I run the same UHD code on both the N200 and the B210. On the N200, full
> scale receive output (ADC is saturated) is 32767. On the B210, full scale
> appears to be 9930. This is at both 4MHz and 8MHz sample rate. The UHD code
> is identical.
>
> Is the full-scale range of the B210 indeed 9930? If not, is there a likely
> reason that I don't see higher values?
>
> Thanks, Sivan
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 10
Date: Mon, 7 Apr 2014 13:20:42 +0100
From: Mike Jameson <[email protected]>
To: Sivan Toledo <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] full-scale range on B210
Message-ID:
<cajcjmirnqevee5iyuwem3c+dzuqu_wqlccw4rpgawwhrsqt...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
I clearly needed another coffee! The negative values are included in the
full scale ADC range so I can only assume the value is doubled due to
complex sampling taking place:
http://www.ni.com/white-paper/3016/en/#toc5
Mike
--
Mike Jameson M0MIK BSc MIET
Email: [email protected]
Web: http://scanoo.com
On Mon, Apr 7, 2014 at 1:00 PM, Mike Jameson <[email protected]> wrote:
> Sivan,
>
> The ADC in a N200 is 14-bit (2**14 = 16384) and the ADC in a B210 is
> 12-bit (2**12 = 4096).
>
> If you multiply the number of quantisation points by two, to include
> negative values (in the time domain), it looks close to what you are seeing.
>
> Mike
>
> --
> Mike Jameson M0MIK BSc MIET
> Email: [email protected]
> Web: http://scanoo.com
>
>
> On Mon, Apr 7, 2014 at 8:29 AM, Sivan Toledo <[email protected]> wrote:
>
>> Hi,
>>
>> I run the same UHD code on both the N200 and the B210. On the N200, full
>> scale receive output (ADC is saturated) is 32767. On the B210, full scale
>> appears to be 9930. This is at both 4MHz and 8MHz sample rate. The UHD code
>> is identical.
>>
>> Is the full-scale range of the B210 indeed 9930? If not, is there a
>> likely reason that I don't see higher values?
>>
>> Thanks, Sivan
>>
>> _______________________________________________
>> USRP-users mailing list
>> [email protected]
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>>
>
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Message: 11
Date: Mon, 7 Apr 2014 13:26:00 +0100
From: Mike Jameson <[email protected]>
To: Sivan Toledo <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] full-scale range on B210
Message-ID:
<CAJcjmiTRT3efOesgh1vLSQWN=t8xv11cub_humniflx+6tj...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
See page 3, paragraph 2.2.4 of the following paper I just discovered which
explains that the number is doubled due to complex sampling:
http://conferences.sigcomm.org/sigcomm/2013/papers/srif/p61.pdf
Mike
--
Mike Jameson M0MIK BSc MIET
Email: [email protected]
Web: http://scanoo.com
On Mon, Apr 7, 2014 at 1:20 PM, Mike Jameson <[email protected]> wrote:
> I clearly needed another coffee! The negative values are included in the
> full scale ADC range so I can only assume the value is doubled due to
> complex sampling taking place:
>
> http://www.ni.com/white-paper/3016/en/#toc5
>
> Mike
>
> --
> Mike Jameson M0MIK BSc MIET
> Email: [email protected]
> Web: http://scanoo.com
>
>
> On Mon, Apr 7, 2014 at 1:00 PM, Mike Jameson <[email protected]> wrote:
>
>> Sivan,
>>
>> The ADC in a N200 is 14-bit (2**14 = 16384) and the ADC in a B210 is
>> 12-bit (2**12 = 4096).
>>
>> If you multiply the number of quantisation points by two, to include
>> negative values (in the time domain), it looks close to what you are seeing.
>>
>> Mike
>>
>> --
>> Mike Jameson M0MIK BSc MIET
>> Email: [email protected]
>> Web: http://scanoo.com
>>
>>
>> On Mon, Apr 7, 2014 at 8:29 AM, Sivan Toledo <[email protected]> wrote:
>>
>>> Hi,
>>>
>>> I run the same UHD code on both the N200 and the B210. On the N200, full
>>> scale receive output (ADC is saturated) is 32767. On the B210, full scale
>>> appears to be 9930. This is at both 4MHz and 8MHz sample rate. The UHD code
>>> is identical.
>>>
>>> Is the full-scale range of the B210 indeed 9930? If not, is there a
>>> likely reason that I don't see higher values?
>>>
>>> Thanks, Sivan
>>>
>>> _______________________________________________
>>> USRP-users mailing list
>>> [email protected]
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>>
>>
>
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Message: 12
Date: Mon, 7 Apr 2014 06:45:36 -0700
From: Dan Sego <[email protected]>
To: [email protected]
Subject: [USRP-users] N200 or N210 with baseband input
Message-ID:
<CALGEVjsXjDGWPYN0TvkkCCtFbguFxsq=syjnrrkaiyscrvn...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Good morning.
Is it possible to operate either the N200 or N210 with a direct baseband
input? Bypassing a tuner card or similar?
cheers,
Dan Sego
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Message: 13
Date: Mon, 7 Apr 2014 14:56:44 +0100
From: Mike Jameson <[email protected]>
To: Dan Sego <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] N200 or N210 with baseband input
Message-ID:
<cajcjmit2z++sw8wzp-1f1gcka8cbt5mt7+dpcyvweraj3vg...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Dan,
The BasicRX is the daughterboard which provides direct access to the ADC
inputs as you have requested:
https://www.ettus.com/product/details/BasicRX
Mike
--
Mike Jameson M0MIK BSc MIET
Email: [email protected]
Web: http://scanoo.com
On Mon, Apr 7, 2014 at 2:45 PM, Dan Sego <[email protected]> wrote:
> Good morning.
>
> Is it possible to operate either the N200 or N210 with a direct baseband
> input? Bypassing a tuner card or similar?
>
> cheers,
> Dan Sego
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 14
Date: Mon, 07 Apr 2014 15:57:40 +0200
From: Marcus M?ller <[email protected]>
To: Dan Sego <[email protected]>,[email protected]
Subject: Re: [USRP-users] N200 or N210 with baseband input
Message-ID: <[email protected]>
Content-Type: text/plain; charset=UTF-8
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA512
Hi Dan Sego,
There are the basicTX/RX daughterboards as well as LFTX/EX for that purpose.
Greetings,
Marcus
On April 7, 2014 3:45:36 PM CEST, Dan Sego <[email protected]> wrote:
>Good morning.
>
>Is it possible to operate either the N200 or N210 with a direct
>baseband
>input? Bypassing a tuner card or similar?
>
>cheers,
>Dan Sego
>
>
>------------------------------------------------------------------------
>
>_______________________________________________
>USRP-users mailing list
>[email protected]
>http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
- --
Sent from my Android device with K-9 Mail. Please excuse my brevity.
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------------------------------
Message: 15
Date: Mon, 7 Apr 2014 15:57:42 +0200
From: "Ralph A. Schmid, dk5ras" <[email protected]>
To: "'Dan Sego'" <[email protected]>,
<[email protected]>
Subject: Re: [USRP-users] N200 or N210 with baseband input
Message-ID: <[email protected]>
Content-Type: text/plain; charset="us-ascii"
Sure, by using the daughterboards LFRX/LFTX.
Ralph.
From: USRP-users [mailto:[email protected]] On Behalf Of
Dan Sego
Sent: Monday, April 7, 2014 3:46 PM
To: [email protected]
Subject: [USRP-users] N200 or N210 with baseband input
Good morning.
Is it possible to operate either the N200 or N210 with a direct baseband
input? Bypassing a tuner card or similar?
cheers,
Dan Sego
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Message: 16
Date: Mon, 7 Apr 2014 15:59:47 +0200
From: "Ralph A. Schmid, dk5ras" <[email protected]>
To: "'Mike Jameson'" <[email protected]>, "'Dan Sego'"
<[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] N200 or N210 with baseband input
Message-ID: <[email protected]>
Content-Type: text/plain; charset="us-ascii"
Be careful with this one - no DC! The real direct path is only possible with
LFRX/LFTX.
Ralph.
From: USRP-users [mailto:[email protected]] On Behalf Of
Mike Jameson
Sent: Monday, April 7, 2014 3:57 PM
To: Dan Sego
Cc: [email protected]
Subject: Re: [USRP-users] N200 or N210 with baseband input
Dan,
The BasicRX is the daughterboard which provides direct access to the ADC
inputs as you have requested:
https://www.ettus.com/product/details/BasicRX
Mike
--
Mike Jameson M0MIK BSc MIET
Email: [email protected] <mailto:[email protected]>
Web: http://scanoo.com
On Mon, Apr 7, 2014 at 2:45 PM, Dan Sego <[email protected]
<mailto:[email protected]> > wrote:
Good morning.
Is it possible to operate either the N200 or N210 with a direct baseband
input? Bypassing a tuner card or similar?
cheers,
Dan Sego
_______________________________________________
USRP-users mailing list
[email protected] <mailto:[email protected]>
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 17
Date: Mon, 7 Apr 2014 15:05:02 +0100
From: Mike Jameson <[email protected]>
To: "Ralph A. Schmid, dk5ras" <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] N200 or N210 with baseband input
Message-ID:
<cajcjmitkog4_oraynld97qp_xmxlgpsa59vaefdks2zgenw...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Good point Ralph!
Here's the url for the LFRX:
https://www.ettus.com/product/details/LFRX
Mike
--
Mike Jameson M0MIK BSc MIET
Email: [email protected]
Web: http://scanoo.com
On Mon, Apr 7, 2014 at 2:59 PM, Ralph A. Schmid, dk5ras <[email protected]>wrote:
> Be careful with this one - no DC! The real direct path is only possible
> with LFRX/LFTX...
>
>
>
> Ralph.
>
>
>
>
>
> *From:* USRP-users [mailto:[email protected]] *On Behalf
> Of *Mike Jameson
> *Sent:* Monday, April 7, 2014 3:57 PM
> *To:* Dan Sego
> *Cc:* [email protected]
> *Subject:* Re: [USRP-users] N200 or N210 with baseband input
>
>
>
> Dan,
>
> The BasicRX is the daughterboard which provides direct access to the ADC
> inputs as you have requested:
>
>
> https://www.ettus.com/product/details/BasicRX
>
> Mike
>
>
> --
> Mike Jameson M0MIK BSc MIET
> Email: [email protected]
> Web: http://scanoo.com
>
>
>
> On Mon, Apr 7, 2014 at 2:45 PM, Dan Sego <[email protected]> wrote:
>
> Good morning.
>
>
>
> Is it possible to operate either the N200 or N210 with a direct baseband
> input? Bypassing a tuner card or similar?
>
>
>
> cheers,
>
> Dan Sego
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
>
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Message: 18
Date: Mon, 7 Apr 2014 17:21:34 +0300
From: Sivan Toledo <[email protected]>
To: Mike Jameson <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] full-scale range on B210
Message-ID:
<caol_rufvorbqcdtn-rh-38h4zg+pcavvgp46wj5brdpgrcv...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Thanks a lot Mike. The strange thing is that the N200, which is also not 16
bits but 14, delivers values that range from -32767 to +32767, so I guess
some scaling is taking place in the N200's FPGA. It seems that the B210 is
doing this differently.
It would be good to specify the full scale values (perhaps using a UHD
call), because it is required for AGC algorithms. This is where I bot
bitten.
On Mon, Apr 7, 2014 at 3:26 PM, Mike Jameson <[email protected]> wrote:
> See page 3, paragraph 2.2.4 of the following paper I just discovered which
> explains that the number is doubled due to complex sampling:
>
> http://conferences.sigcomm.org/sigcomm/2013/papers/srif/p61.pdf
>
> Mike
>
>
> --
> Mike Jameson M0MIK BSc MIET
> Email: [email protected]
> Web: http://scanoo.com
>
>
> On Mon, Apr 7, 2014 at 1:20 PM, Mike Jameson <[email protected]> wrote:
>
>> I clearly needed another coffee! The negative values are included in the
>> full scale ADC range so I can only assume the value is doubled due to
>> complex sampling taking place:
>>
>> http://www.ni.com/white-paper/3016/en/#toc5
>>
>> Mike
>>
>> --
>> Mike Jameson M0MIK BSc MIET
>> Email: [email protected]
>> Web: http://scanoo.com
>>
>>
>> On Mon, Apr 7, 2014 at 1:00 PM, Mike Jameson <[email protected]> wrote:
>>
>>> Sivan,
>>>
>>> The ADC in a N200 is 14-bit (2**14 = 16384) and the ADC in a B210 is
>>> 12-bit (2**12 = 4096).
>>>
>>> If you multiply the number of quantisation points by two, to include
>>> negative values (in the time domain), it looks close to what you are seeing.
>>>
>>> Mike
>>>
>>> --
>>> Mike Jameson M0MIK BSc MIET
>>> Email: [email protected]
>>> Web: http://scanoo.com
>>>
>>>
>>> On Mon, Apr 7, 2014 at 8:29 AM, Sivan Toledo <[email protected]> wrote:
>>>
>>>> Hi,
>>>>
>>>> I run the same UHD code on both the N200 and the B210. On the N200,
>>>> full scale receive output (ADC is saturated) is 32767. On the B210, full
>>>> scale appears to be 9930. This is at both 4MHz and 8MHz sample rate. The
>>>> UHD code is identical.
>>>>
>>>> Is the full-scale range of the B210 indeed 9930? If not, is there a
>>>> likely reason that I don't see higher values?
>>>>
>>>> Thanks, Sivan
>>>>
>>>> _______________________________________________
>>>> USRP-users mailing list
>>>> [email protected]
>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>>
>>>>
>>>
>>
>
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Message: 19
Date: Mon, 7 Apr 2014 07:29:04 -0700
From: Ian Buckley <[email protected]>
To: Adrian Martinez Gomez <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] Achieving higher sampling rates with the
N210 for multi-constellation GNSS record-playback
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
The issue you are seeing is not caused by the FPGA code but is a problem with
the Xilinx tools. ISE is failing to find an executable library that is supplied
with the tools. Have you run /opt/Xilinx/12.2/ISE_DS/settings64.sh (This is the
default install location)?
-Ian
On Apr 7, 2014, at 1:27 AM, Adrian Martinez Gomez <[email protected]>
wrote:
> Hello all,
>
> although I know this is probably no USRP specific question, but rather a
> Xilinx one, I would want to know the opinion of the ones of you who have
> worked with the FPGA code.
>
> What I am trying to do is just to generate the bin file for the FPGA for the
> USRP N210 myself, using the ISE Suite Edition (12.2 version; with 30 day
> trial license).
> I followed the instruction on the README.txt on the fpga folder of
> https://github.com/EttusResearch/uhd/tree/master/fpga
> When running "make -f Makefile.N210R4 bin" I get the following in the
> build.log file, and an empty .bin build:
> Mapping completed.
> See MAP report file u2plus_map.mrp for details.
>
> /opt/Xilinx/12.2/ISE_DS/ISE/bin/lin64/unwrapped/map: symbol lookup error:
> /opt/Xilinx/12.2/ISE_DS/ISE//lib/lin64/libXst_Core.so: undefined symbol:
> _ZN5antlr6BitSetD1Ev
>
> Process "Map" failed
>
> Did someone have the same issue? Some ideas on what might have gone wrong?
> The FPGA code is unmodified, I only wanted to be able to generate the FPGA
> image myself (for future modifications).
>
> Thanks in advance!
>
> P.S. attached you will find my build.log as well as my u2plus_map.mrp (in
> case it helps)
> build.log
>
> u2plus_map.mrp
>
>
> On Thu, Apr 3, 2014 at 4:42 PM, Adrian Martinez Gomez
> <[email protected]> wrote:
> At the end another NIC (already on the PC, just another port) worked just
> fine.
>
> @Marcus. For the time being I will stick with trying to do the reduction on
> the FPGA. The network bandwidth would be also a motivation for doing it this
> way.
>
>
> On Thu, Apr 3, 2014 at 2:14 PM, Martin Braun <[email protected]> wrote:
> On 04/02/2014 03:20 PM, Adrian Martinez Gomez wrote:
> > Quick update:
> > I achieved the 25Msps and sc16 as well as 50Msps and sc8 with some NIC
> > work. Now both rx and tx work fine.
>
> Hi Adrian,
>
> what did you do? Did you try another NIC, or do some configuration?
>
> Martin
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 20
Date: Mon, 7 Apr 2014 07:53:45 -0700
From: Ian Buckley <[email protected]>
To: Sivan Toledo <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] full-scale range on B210
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
OK 2 issues here:
First the concept that Mike introduced that the size of the ADC bus determines
he maximum sample magnitude before overflow will occur. Because we use a range
of converters and integrated radios from 12 through 16bits across products and
also try to re-use the same FPGA modules, we have for usrp2 and usrp3
generations, standardized on the use of a complex sample data type that uses
16bits each for I and Q values, and these values are two's complement signed
format. When a converter is smaller than 16bits we LEFT JUSTIFY the same
smaller bus, in other words we use the MSB bits and truncate (or zero pad for
Rx) the LSB's. Thus code becomes more portable between USRPs. So broadly
speaking Sivan is correct to state that -32768 -> 32767 is the expected maximum
dynamic range.
Now the issue of Sivan's B210 overflowing with a 9930 sample magnitude. That is
unexpected, I have myself recently encountered some B210 overflow issues at
approx 85% of 32768, but nothing as low as this. We do apply a gain value
internally to compensate for the algorithmic gain of the CORDIC algorithm, so
that's one possible area we need to check. The waveform you see this on is of
interest..is it possible you can share this flow graph with us? In general we
do recommend people reserve some headroom when setting there scaling gain for
the samples but not this much.
-Ian
On Apr 7, 2014, at 7:21 AM, Sivan Toledo <[email protected]> wrote:
> Thanks a lot Mike. The strange thing is that the N200, which is also not 16
> bits but 14, delivers values that range from -32767 to +32767, so I guess
> some scaling is taking place in the N200's FPGA. It seems that the B210 is
> doing this differently.
>
> It would be good to specify the full scale values (perhaps using a UHD call),
> because it is required for AGC algorithms. This is where I bot bitten.
>
>
> On Mon, Apr 7, 2014 at 3:26 PM, Mike Jameson <[email protected]> wrote:
> See page 3, paragraph 2.2.4 of the following paper I just discovered which
> explains that the number is doubled due to complex sampling:
>
> http://conferences.sigcomm.org/sigcomm/2013/papers/srif/p61.pdf
>
> Mike
>
>
> --
> Mike Jameson M0MIK BSc MIET
> Email: [email protected]
> Web: http://scanoo.com
>
>
> On Mon, Apr 7, 2014 at 1:20 PM, Mike Jameson <[email protected]> wrote:
> I clearly needed another coffee! The negative values are included in the full
> scale ADC range so I can only assume the value is doubled due to complex
> sampling taking place:
>
> http://www.ni.com/white-paper/3016/en/#toc5
>
> Mike
>
> --
> Mike Jameson M0MIK BSc MIET
> Email: [email protected]
> Web: http://scanoo.com
>
>
> On Mon, Apr 7, 2014 at 1:00 PM, Mike Jameson <[email protected]> wrote:
> Sivan,
>
> The ADC in a N200 is 14-bit (2**14 = 16384) and the ADC in a B210 is 12-bit
> (2**12 = 4096).
>
> If you multiply the number of quantisation points by two, to include negative
> values (in the time domain), it looks close to what you are seeing.
>
> Mike
>
> --
> Mike Jameson M0MIK BSc MIET
> Email: [email protected]
> Web: http://scanoo.com
>
>
> On Mon, Apr 7, 2014 at 8:29 AM, Sivan Toledo <[email protected]> wrote:
> Hi,
>
> I run the same UHD code on both the N200 and the B210. On the N200, full
> scale receive output (ADC is saturated) is 32767. On the B210, full scale
> appears to be 9930. This is at both 4MHz and 8MHz sample rate. The UHD code
> is identical.
>
> Is the full-scale range of the B210 indeed 9930? If not, is there a likely
> reason that I don't see higher values?
>
> Thanks, Sivan
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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*****************************************
