Send USRP-users mailing list submissions to
[email protected]
To subscribe or unsubscribe via the World Wide Web, visit
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
or, via email, send a message with subject or body 'help' to
[email protected]
You can reach the person managing the list at
[email protected]
When replying, please edit your Subject line so it is more specific
than "Re: Contents of USRP-users digest..."
Today's Topics:
1. Which approach to use for adding new components in USRP's
FPGA ? (Anum Sheraz via USRP-users)
----------------------------------------------------------------------
Message: 1
Date: Fri, 18 Apr 2014 17:31:32 +0000 (UTC)
From: Anum Sheraz via USRP-users <[email protected]>
To: [email protected]
Subject: [USRP-users] Which approach to use for adding new components
in USRP's FPGA ?
Message-ID: <[email protected]>
Content-Type: text/plain; charset=us-ascii
Hi,
1. Changing HDL codes directly from source file (verilog).
2. Using LABView FPGA for this ?
3. Using MATLAB Simulink approach ?
As the default FPGA source code also contains the UHD drivers controllers, so
we wont erase the existing code. for this reason, the (number 1) approach can
be used.
but I was thinking that if i need to add some additional functions to the FPGA
block of USRP. can i use LABView FPGA or SIMULINK (Xilinx System Generator) to
make the design first, convert it into HDL codes, create bit file and upload
its image into the USRP's FPGA. Will that be possible ?
------------------------------
Subject: Digest Footer
_______________________________________________
USRP-users mailing list
[email protected]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
------------------------------
End of USRP-users Digest, Vol 44, Issue 19
******************************************
