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Today's Topics:
1. Re: Confused about the definition of naming pins in FPGA code
(Isen I-Chun Chao)
2. Need advice to find out the appropriate place in module radio
of X310 FPGA code to observe sample streams (Isen I-Chun Chao)
3. Re: Need advice to find out the appropriate place in module
radio of X310 FPGA code to observe sample streams (Ian Buckley)
4. Re: Need advice to find out the appropriate place in module
radio of X310 FPGA code to observe sample streams (Isen I-Chun Chao)
----------------------------------------------------------------------
Message: 1
Date: Sat, 4 Oct 2014 20:36:31 -0400
From: Isen I-Chun Chao <[email protected]>
To: Ashish Chaudhari <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] Confused about the definition of naming pins
in FPGA code
Message-ID:
<CAEG73KoZyB0EsCN=bAtA=azcopxvfhlotgfyqhrbowpfe-a...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Thanks Ashish,
It does help me figure it out.
*Best Regards,Isen I-Chun Chao*
On Fri, Oct 3, 2014 at 7:33 PM, Ashish Chaudhari <[email protected]
> wrote:
> Hi Isen,
>
> The signals that you are looking at are a part of the AMBA AXI4-Stream
> Interface [1] that is used widely in the X3x0 design. Several signals have
> to come together to form a "stream" and they are not in the same direction.
> For instance, if you have an AXI stream going from A to B then you would
> have the following signals:
> - tdata: Data asserted by A for consumption by B
> - tvalid: If asserted then the data on the "tdata" bus is valid
> - tlast: If asserted then this is the last word in the burst/packet/frame
> - tready: If asserted then B is ready to consume more data from A
>
> tdata, tvalid and tlast go from A->B and tready goes from B->A. Data is
> only transferred when tvalid and tready are both asserted. The "i_" and
> "o_" prefixes on the data just indicate the direction of the stream where
> 'i' means input and 'o' means output. For example, i_tvalid refers to the
> tvalid signal for the input stream for a particular block, and it should be
> an "input" port. Similarly o_tready refers to the tready signal for the
> output stream which is also an input port.
>
> Hope that helps clear things up.
>
> [1]
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0051a/index.html
>
> *Ashish Chaudhari* | Senior Software Engineer | High Frequency
> Measurements - RF
> Ettus Research, *A National Instruments Company*
> [email protected]
>
> On Fri, Oct 3, 2014 at 12:27 PM, Isen I-Chun Chao via USRP-users <
> [email protected]> wrote:
>
>> Hi
>> I am digging into the '*radio.v*' of X310 FPGA code. When I traced it
>> into module '*axi_fifo_short*', I am so confused about the definition of
>> "*i_tvalid*", "*o_tready*", which are inputs, and "*i_tready*", "
>> *o_tvalid*", which are outputs. This four signals are used throughout
>> radio module.
>>
>>
>> Also, if the range of the register '*a*' is from 0 to 30, is that mean
>> this FIFO (*axi_fifo_short*) is only 31 length?
>>
>> Thanks.
>>
>>
>>
>> *Best Regards,Isen I-Chun Chao*
>>
>> _______________________________________________
>> USRP-users mailing list
>> [email protected]
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>>
>
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Message: 2
Date: Sun, 5 Oct 2014 01:38:10 -0400
From: Isen I-Chun Chao <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] Need advice to find out the appropriate place in
module radio of X310 FPGA code to observe sample streams
Message-ID:
<caeg73kogj-fhhqwxby7jyv2hxuzvb5tniccyijsymwdwr98...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi,
I am tracing *radio.v *of X310 FPGA code and trying to figure out the data
path and control path so I can find an appropriate place of observing the
incoming sample stream from ADC and outgoing sample stream to DAC. We hope
to add a customized module which can monitor both sample streams and create
timestamp information for application layers. However, since I only can
learn how this module, *radio.v*, works by viewing the source code, which
is more complicated than I thought, I am actually lost in it.
For example in rx path, I did find there is signals from '*rx_dsp.ddc_chain*'
called *samples[31:0]* connecting to the module '*new_rx_framer*' to
produce *o_tdata[63:0]*, but then I can't figure out the operating logic in
the rest of modules, such as module '*new_rx_control*', '*rx_sfc*', ...,
this signal go through.
Maybe based on what we need we don't have to understand each part in
*radio.v*, and we just need to know how some critical subsets of this
module works to achieve our objective? Or we just need to know where is the
right place for adding our customized module?
As the matter of fact, we have spent few weeks on it and so far we have no
progress. Could anyone please advise me? I would very appreciate it.
Thanks
*Best Regards,Isen I-Chun Chao*
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Message: 3
Date: Sun, 5 Oct 2014 00:40:11 -0700
From: Ian Buckley <[email protected]>
To: Isen I-Chun Chao <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] Need advice to find out the appropriate
place in module radio of X310 FPGA code to observe sample streams
Message-ID: <[email protected]>
Content-Type: text/plain; charset="us-ascii"
Do you want to observe a sample stream at the ADC/DAC rate or the sample rate
over-the-wire to UHD/GNURadio?
On Oct 4, 2014, at 10:38 PM, Isen I-Chun Chao via USRP-users
<[email protected]> wrote:
> Hi,
> I am tracing radio.v of X310 FPGA code and trying to figure out the data path
> and control path so I can find an appropriate place of observing the incoming
> sample stream from ADC and outgoing sample stream to DAC. We hope to add a
> customized module which can monitor both sample streams and create timestamp
> information for application layers. However, since I only can learn how this
> module, radio.v, works by viewing the source code, which is more complicated
> than I thought, I am actually lost in it.
>
> For example in rx path, I did find there is signals from 'rx_dsp.ddc_chain'
> called samples[31:0] connecting to the module 'new_rx_framer' to produce
> o_tdata[63:0], but then I can't figure out the operating logic in the rest of
> modules, such as module 'new_rx_control', 'rx_sfc', ..., this signal go
> through.
>
> Maybe based on what we need we don't have to understand each part in radio.v,
> and we just need to know how some critical subsets of this module works to
> achieve our objective? Or we just need to know where is the right place for
> adding our customized module?
>
> As the matter of fact, we have spent few weeks on it and so far we have no
> progress. Could anyone please advise me? I would very appreciate it.
>
> Thanks
>
>
> Best Regards,
> Isen I-Chun Chao
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 4
Date: Sun, 5 Oct 2014 07:46:07 -0400
From: Isen I-Chun Chao <[email protected]>
To: Ian Buckley <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] Need advice to find out the appropriate
place in module radio of X310 FPGA code to observe sample streams
Message-ID:
<caeg73kpncd5gcwtfr9ljwfnysurswm5vs6zxr8yzf151cdf...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi Ian,
Thanks for responding. I thinks the last one (observing it at the sample
rate) is what we are looking for.
Once we can observe the sample streams and create a timestamp for a regular
packet from Tx to Rx (by observing sample streams), we need to be able to
access it either from default UHD APIs or from extended/customized UHD APIs.
*Best Regards,Isen I-Chun Chao*
On Sun, Oct 5, 2014 at 3:40 AM, Ian Buckley <[email protected]> wrote:
> Do you want to observe a sample stream at the ADC/DAC rate or the sample
> rate over-the-wire to UHD/GNURadio?
>
> On Oct 4, 2014, at 10:38 PM, Isen I-Chun Chao via USRP-users <
> [email protected]> wrote:
>
> Hi,
> I am tracing *radio.v *of X310 FPGA code and trying to figure out the
> data path and control path so I can find an appropriate place of observing
> the incoming sample stream from ADC and outgoing sample stream to DAC. We
> hope to add a customized module which can monitor both sample streams and
> create timestamp information for application layers. However, since I only
> can learn how this module, *radio.v*, works by viewing the source code,
> which is more complicated than I thought, I am actually lost in it.
>
> For example in rx path, I did find there is signals from '
> *rx_dsp.ddc_chain*' called *samples[31:0]* connecting to the module '
> *new_rx_framer*' to produce *o_tdata[63:0]*, but then I can't figure out
> the operating logic in the rest of modules, such as module '
> *new_rx_control*', '*rx_sfc*', ..., this signal go through.
>
> Maybe based on what we need we don't have to understand each part in
> *radio.v*, and we just need to know how some critical subsets of this
> module works to achieve our objective? Or we just need to know where is the
> right place for adding our customized module?
>
> As the matter of fact, we have spent few weeks on it and so far we have no
> progress. Could anyone please advise me? I would very appreciate it.
>
> Thanks
>
>
>
> *Best Regards,Isen I-Chun Chao*
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
>
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