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Today's Topics:
1. Re: Description of Timestamp & I/Q samples out of the radio &
CHDR (Ian Buckley)
2. Re: USRP X310 motherboard issues (Marcus M?ller)
3. Re: USRP X310 motherboard issues (Matt Ettus)
----------------------------------------------------------------------
Message: 1
Date: Wed, 10 Dec 2014 10:39:32 -0800
From: Ian Buckley <[email protected]>
To: [email protected]
Cc: [email protected]
Subject: Re: [USRP-users] Description of Timestamp & I/Q samples out
of the radio & CHDR
Message-ID: <[email protected]>
Content-Type: text/plain; charset="windows-1252"
Seb,
Try referring to this document for now, its written from an IC design
perspective.
http://ionconcepts.com/files/USRP3_concepts.pdf
-Ian
On Dec 10, 2014, at 6:06 AM, seb fenn via USRP-users
<[email protected]> wrote:
> Martin
>
> Many thanks for your answers.
>
> When you refer to 'The Manual' are you referring to this:
>
> http://files.ettus.com/manual/
>
> The point I was trying to make that I am attempting to add custom logic into
> the FPGA fabric itself. To successfully do this, I need to know EXACTLY the
> format of data returned over the AXI bus (CHDR data). Looking at software
> APIs doesn't tell me how this data is structured on the AXI streaming bus, or
> what it means. For example I need to know which entry in the packet the
> timestamp is so I can trap it in my logic (I think it is the second word BTW).
>
> Unless I am completely missing some source of information, it feels as though
> all I can do is simulate the radio in a VHDL/Verilog testbench, assuming I
> can work out how to configure it in my testbench. (Or try to work it out from
> the Verilog).
>
> BTW I have just come across this:
>
> Which explains the CHDR format in more detail than I have previously seen.
>
> https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/vita_chdr.txt
>
> Many thanks
>
> Seb
>
>
>
>> Hey Sebastian,
>>
>> thanks for checking out RFNoC. I have answers inline.
>>
>> On 12/10/2014 11:22 AM, seb fenn via USRP-users wrote:
>>> Hi
>>>
>>> Can someone please refer me to some accurate documentation, or
>>> describe, the structure of (CHDR) data coming out of the radio and
>>> into the RFNoC network. In particular:
>>
>> CHDR is described in the manual. You'll need to use your local build of
>> the UHD manual when working with RFNoC.
>>
>>> a) What is the format of the timestamp
>>
>> It counts ticks.
>>
>>> b) Where is the timestamp is the packet
>>
>> See the manual. Also, I recommend the CHDR dissectors for wireshark.
>>
>>> c) How the I and Q samples are arranged in the 64 bit words d) Size
>>> and coding of the I/Q samples (e.g. 16 bit signed?)
>>
>> CHDR does by itself not define the data type; the assumption is that the
>> the block knows what to do with the data.
>> For our typical operations, we use 16-bit signed (as indicated by the
>> "sc16" data description).
>>
>>> e) What is a trailer (as indicated by bit 62 in the header)
>>
>> CHDR does not have a trailer. Bit 62 is part of the packet type (see the
>> manual).
>>
>>> I am coding up blocks to include in the FPGA fabric, not writing
>>> software.
>>
>> Until we've finished all of our RFNoC goals, you'll probably need to do
>> both -- although for starters, adding an XML stub in
>> uhd/usrp/rfnoc/blocks/ will probably do.
>>
>>> And is there more information on CHDR? I have gleaned some from
>>> simulations and the paper "Simplifying FPGA Design with a Novel
>>> Network on Chip Architecture". But could do with some more complete
>>> descriptions. For example I don't understand why the Packet Size
>>> field in Context Packets in various testbenches (e.g. noc_shell_tb.v)
>>> is set to 16. And there seems to be a three word acknowledgment of a
>>> write to the NoC Shell address space. What is the meaning of the data
>>> in these words, I have guessed some of it , but would like
>>> confirmation.
>>
>> 'context package' is actually a VITA-49 term. It still means the same
>> here, although in CHDR, we can know name all the packet types specifically.
>>
>>> I have seen
>>> https://github.com/EttusResearch/uhd/wiki/RFNoC:--Specification , but
>>> more information would be welcomed. For example is there any guidance
>>> on the usage of the "Upstream Flow Control: Cycles per ACK" and
>>> "Downstream Flow Control: Buffer size" registers? Some of this
>>> information seems inaccurate, for example the " Upstream Flow
>>> Control: Packets per ACK" register seems to be tied low.
>>>
>>> Thanks in advance. The RFNoC approach seems a great innovation but
>>> working out how to add my own logic is proving something of a slog at
>>> the moment and I'd welcome more documentation.
>>
>> At this time, all we can offer is the entirety of our sources. Also, the
>> C++ API documentation is fairly complete, and also answers some of your
>> questions on nomenclature.
>>
>> I guess what you really want is a step-by-step tutorial, and I agree it
>> would be nice to have all that. But doing that is would be a waste of
>> everyone's time until all APIs etc. have been finalized -- also, it
>> would slow down the active development, which is still going on at full
>> pace, be assured!
>>
>> Cheers,
>> Martin
>
>
>
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Message: 2
Date: Wed, 10 Dec 2014 20:30:12 +0100
From: Marcus M?ller <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] USRP X310 motherboard issues
Message-ID: <[email protected]>
Content-Type: text/plain; charset="windows-1252"
Hello Tim,
this is in fact quite a bit surprising. I have no idea where the 500kHz
spaced tones in your QPSK_B.png came from, so I'm really just guessing
around how to narrow down reasons:
The numeric values seem to be low, but I want to be on the safe side:
* How much input power are you providing (please make sure to stay below
-15dBm!)?
* If you reduce input power/voltage, does the effect decrease?
* Does it get worse when you increase the analog gain?
* could you please tune to let's say 303.25MHz?
* If you run the osmocom Spectrum Browser with
-a "lo_offset=15000000"
does the picture change dramatically?
This is all very generic... I can't really explain the little spikes in
your multi_tone_B.png, so far.
Between the daughterboard and the ADC is only a (if I remember
correctly) 6GHz RC lowpass; so no active active parts that would explain
these spikes.#
I hope this can be solved fast!
Best regards,
Marcus M?ller
On 12/10/2014 07:02 PM, Timothy Schaffer via USRP-users wrote:
> I received an X310 from NI last week along with 2 x WBX-120 boards and I've
> noticed a difference in signal quality between the A and B subdevs of the
> motherboard. Overall, It seems the signals receive from the B side are
> generally distorted and prone to harmonics. I naturally assumed this was an
> issue with the WBX boards, so I swapped them and noticed the same issues.
> Next I swapped the cables connected to the bulkhead and still the same
> issue.
> I''m currently using UHD 3.008.000-52, but have not tried other versions.
> I've reloaded the FPGA firmware, ran all 3 cal routines on both subdevs.
> I'm not sure what else to try? I'v eattached a couple of screen shots of
> some of the tests I performed with an HP E4432B. The tests were done back
> to back using the same cable from the siggen to the USRP.
>
> You can see in these two screen shots, the actual distortion to the
> waveform in the scope.
> [image: Inline image 2].[image: Inline image 1]
>
> Here is a DQPSK(24.3ksps) test signal at 303 MHz
>
> [image: Inline image 3][image: Inline image 4]
>
> Any ideas on what could be wrong, or does it need to go back to NI for
> repair/replace?
>
> -Tim
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 3
Date: Wed, 10 Dec 2014 11:37:18 -0800
From: Matt Ettus <[email protected]>
To: Timothy Schaffer <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] USRP X310 motherboard issues
Message-ID:
<CAN=1kn-E=1no24jxw3use9zrguz0+fbni1+u9-avshngooa...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Tim,
This is actually caused by a timing problem that crept into the FPGA builds
because we had an unconstrained path. What you are seeing is signals
passing between clock domains and sometimes a few bits don't make it in
time so you get a glitch. We noticed it a few days ago, and have fixed
it. We are building new images in all the variations, and the new builds
will be available tomorrow. Sorry for the inconvenience.
Thanks,
Matt
On Wed, Dec 10, 2014 at 10:02 AM, Timothy Schaffer via USRP-users <
[email protected]> wrote:
> I received an X310 from NI last week along with 2 x WBX-120 boards and
> I've noticed a difference in signal quality between the A and B subdevs of
> the motherboard. Overall, It seems the signals receive from the B side are
> generally distorted and prone to harmonics. I naturally assumed this was an
> issue with the WBX boards, so I swapped them and noticed the same issues.
> Next I swapped the cables connected to the bulkhead and still the same
> issue.
> I''m currently using UHD 3.008.000-52, but have not tried other versions.
> I've reloaded the FPGA firmware, ran all 3 cal routines on both subdevs.
> I'm not sure what else to try? I'v eattached a couple of screen shots of
> some of the tests I performed with an HP E4432B. The tests were done back
> to back using the same cable from the siggen to the USRP.
>
> You can see in these two screen shots, the actual distortion to the
> waveform in the scope.
> [image: Inline image 2].[image: Inline image 1]
>
> Here is a DQPSK(24.3ksps) test signal at 303 MHz
>
> [image: Inline image 3][image: Inline image 4]
>
> Any ideas on what could be wrong, or does it need to go back to NI for
> repair/replace?
>
> -Tim
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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