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Today's Topics:
1. Errors when building X310_RFNOC_HGS in X300 for rfnoc-ofdm
branch (Swanson, Craig)
2. Re: E310 (RFNoC not PC host) (Ignazio Finazzi)
3. Re: E310 (RFNoC not PC host) (Ignazio Finazzi)
4. Re: E310 (RFNoC not PC host) (Philip Balister)
----------------------------------------------------------------------
Message: 1
Date: Sat, 9 Apr 2016 19:09:22 +0000
From: "Swanson, Craig" <[email protected]>
To: Jonathon Pendlum <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: [USRP-users] Errors when building X310_RFNOC_HGS in X300 for
rfnoc-ofdm branch
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
Jonathon,
Here are my errors when I executed the following:
~/uhd/rfnoc-ofdm/usrp3/top/x300 (rfnoc-devel)$ make X310_RFNOC_HGS
?
ERROR: [Synth 8-439] module 'divide_int16_int32' not found
[/home/craig/uhd/rfnoc-ofdm/usrp3/lib/rfnoc/complex_invert.v:94]
ERROR: [Synth 8-285] failed synthesizing module 'complex_invert'
[/home/craig/uhd/rfnoc-ofdm/usrp3/lib/rfnoc/complex_invert.v:10]
ERROR: [Synth 8-285] failed synthesizing module 'one_tap_equalizer'
[/home/craig/uhd/rfnoc-ofdm/usrp3/lib/rfnoc/one_tap_equalizer.v:5]
ERROR: [Synth 8-285] failed synthesizing module 'noc_block_eq'
[/home/craig/uhd/rfnoc-ofdm/usrp3/lib/rfnoc/noc_block_eq.v:5]
ERROR: [Synth 8-285] failed synthesizing module 'x300_core'
[/home/craig/uhd/rfnoc-ofdm/usrp3/top/x300/x300_core.v:2]
INFO: [Synth 8-4472] Detected and applied attribute dont_touch =
32'b00000000000000000000000000000000
[/home/craig/uhd/rfnoc-ofdm/usrp3/top/x300/x300.v:1367]
ERROR: [Synth 8-285] failed synthesizing module 'x300'
[/home/craig/uhd/rfnoc-ofdm/usrp3/top/x300/x300.v:18]
Craig F. Swanson
Research Engineer II
Information and Communications Laboratory
Communications, Systems, and Spectrum Division
Georgia Tech Research Institute
Room 560
250 14th St NW
Atlanta, GA 30318
Cell: 770.298.9156
http://www.gtri.gatech.edu<https://mail.gtri.gatech.edu/owa/redir.aspx?C=c20925f2f0af4dd29329ddf0701ecfff&URL=http%3a%2f%2fwww.gtri.gatech.edu%2f>
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Message: 2
Date: Sun, 10 Apr 2016 07:07:10 +0000 (UTC)
From: Ignazio Finazzi <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] E310 (RFNoC not PC host)
Message-ID: <[email protected]>
Content-Type: text/plain; charset=utf-8
Matt Ettus via USRP-users <usrp-users@...> writes:
>
>
>
> On Fri, Apr 8, 2016 at 8:57 PM, Marcus M?ller <usrp-users <at>
lists.ettus.com> wrote:
> > If not, how can i develop programs within the FPGA without VHDL or
> Verilog?I'm afraid that in its current state, this is not really possible. You
> will need at least basic Verilog proficiency.
> Best regards,
> Marcus
>
>
> Actually, you can use Vivado HLS to create blocks with C instead of
Verilog/VHDL.? See the add_sub block in the rfnoc directory.
>
> Matt
>
>
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@...
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
Thanks Matt
I have installed Webpack but i think i need the JTAG Xilin tool, i'm rigth?
In order to use RFNoC native blocks i need to crosscompile UHD RFNoC branch
and crosscompile gr-ettus or can i compile both on the ARM (I think that the
secondone is slower)?
Thanks both, and congratulations for your amazing projects (GNURadio and
USRP) there are two powerful tools for signal system development.
------------------------------
Message: 3
Date: Sun, 10 Apr 2016 08:36:51 +0000 (UTC)
From: Ignazio Finazzi <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] E310 (RFNoC not PC host)
Message-ID: <[email protected]>
Content-Type: text/plain; charset=utf-8
Ignazio Finazzi via USRP-users <usrp-users@...> writes:
>
> Matt Ettus via USRP-users <usrp-users <at> ...> writes:
>
> >
> >
> >
> > On Fri, Apr 8, 2016 at 8:57 PM, Marcus M?ller <usrp-users <at>
> lists.ettus.com> wrote:
> > > If not, how can i develop programs within the FPGA without VHDL or
> > Verilog?I'm afraid that in its current state, this is not really
possible. You
> > will need at least basic Verilog proficiency.
> > Best regards,
> > Marcus
> >
> >
> > Actually, you can use Vivado HLS to create blocks with C instead of
> Verilog/VHDL.? See the add_sub block in the rfnoc directory.
> >
> > Matt
> >
> >
> >
> >
> > _______________________________________________
> > USRP-users mailing list
> > USRP-users <at> ...
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> >
>
> Thanks Matt
>
> I have installed Webpack but i think i need the JTAG Xilin tool, i'm rigth?
>
> In order to use RFNoC native blocks i need to crosscompile UHD RFNoC branch
> and crosscompile gr-ettus or can i compile both on the ARM (I think that the
> secondone is slower)?
>
> Thanks both, and congratulations for your amazing projects (GNURadio and
> USRP) there are two powerful tools for signal system development.
>
> _______________________________________________
> USRP-users mailing list
> USRP-users <at> lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
One more question. In order to getting started in RFNoC i have tried to
connect by Network Mode.
First of all i updated my SDimage to release 4 version. Second rebuilt and
reinstall UHD enabling Network mode on E300. Third, set the device ip
address to static 192.168.1.123 and finally launch network mode on the
device (usrp_e3x0_network_mode; after doing that all RX-TX leds turned on).
And when i run my flow graph (on my PC) y get an error:
linux; GNU C++ version 4.8.4; Boost_105400; UHD_003.010.rfnoc-316-gb7546712
-- Initializing core control...
-- Performing register loopback test... pass
Traceback (most recent call last):
File "/home/ignazio/top_block.py", line 158, in <module>
main()
File "/home/ignazio/top_block.py", line 146, in main
tb = top_block_cls()
File "/home/ignazio/top_block.py", line 69, in __init__
channels=range(1),
File "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/__init__.py",
line 122, in constructor_interceptor
return old_constructor(*args)
File "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/uhd_swig.py",
line 2239, in make
return _uhd_swig.usrp_source_make(*args)
RuntimeError: RuntimeError: Expected FPGA compatibility number 255.x, but
got 14.0:
The FPGA build is not compatible with the host code build.
Please run:
"/usr/local/lib/uhd/utils/uhd_images_downloader.py"
>>> Done
After run uhd_images_downloader.py the error is the same.
When i look for USRP devices the output is:
ignazio@Heimdall:/usr/local/lib/uhd/utils$ uhd_find_devices
linux; GNU C++ version 4.8.4; Boost_105400; UHD_003.010.rfnoc-316-gb7546712
--------------------------------------------------
-- UHD Device 0
--------------------------------------------------
Device Address:
type: e3x0
addr: 192.168.1.123
name:
serial: 30B0160
product: 30674
And, in the E310 terminal:
root@ettus-e3xx-sg1:~# usrp_e3x0_network_mode
linux; GNU C++ version 4.9.2; Boost_105700; UHD_003.009.002-0-unknown
-- Loading FPGA image: /usr/share/uhd/images/usrp_e310_fpga.bit... done
-- e300 run server on port 21756 for RX
-- e300 socket accept on port 21756 for RX
-- e300 run server on port 21762 for SENSOR
-- e300 run server on port 21857 for TX
-- e300 run server on port 21858 for CTRL
-- e300 run server on port 21761 for I2C
-- e300 run server on port 21856 for RX
-- e300 socket accept on port 21857 for TX
-- e300 run server on port 21757 for TX
-- e300 socket accept on port 21757 for TX
-- e300 socket accept on port 21858 for CTRL
-- e300 run server on port 21758 for CTRL
-- e300 socket accept on port 21758 for CTRL
-- e300 socket accept on port 21761 for I2C
-- e300 socket accept on port 21762 for SENSOR
-- e300 run server on port 21760 for GREGS
-- e300 socket accept on port 21760 for GREGS
-- e300 socket accept on port 21856 for RX
-- e300 run server on port 21759 for CODEC
-- e300 socket accept on port 21759 for CODEC
Thanks all
------------------------------
Message: 4
Date: Sun, 10 Apr 2016 08:18:53 -0400
From: Philip Balister <[email protected]>
To: Ignazio Finazzi <[email protected]>,
[email protected]
Subject: Re: [USRP-users] E310 (RFNoC not PC host)
Message-ID: <[email protected]>
Content-Type: text/plain; charset=utf-8
On 04/10/2016 04:36 AM, Ignazio Finazzi via USRP-users wrote:
> Ignazio Finazzi via USRP-users <usrp-users@...> writes:
>
>>
>> Matt Ettus via USRP-users <usrp-users <at> ...> writes:
>>
>>>
>>>
>>>
>>> On Fri, Apr 8, 2016 at 8:57 PM, Marcus M?ller <usrp-users <at>
>> lists.ettus.com> wrote:
>>>> If not, how can i develop programs within the FPGA without VHDL or
>>> Verilog?I'm afraid that in its current state, this is not really
> possible. You
>>> will need at least basic Verilog proficiency.
>>> Best regards,
>>> Marcus
>>>
>>>
>>> Actually, you can use Vivado HLS to create blocks with C instead of
>> Verilog/VHDL. See the add_sub block in the rfnoc directory.
>>>
>>> Matt
>>>
>>>
>>>
>>>
>>> _______________________________________________
>>> USRP-users mailing list
>>> USRP-users <at> ...
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>
>> Thanks Matt
>>
>> I have installed Webpack but i think i need the JTAG Xilin tool, i'm rigth?
>>
>> In order to use RFNoC native blocks i need to crosscompile UHD RFNoC branch
>> and crosscompile gr-ettus or can i compile both on the ARM (I think that the
>> secondone is slower)?
>>
>> Thanks both, and congratulations for your amazing projects (GNURadio and
>> USRP) there are two powerful tools for signal system development.
>>
>> _______________________________________________
>> USRP-users mailing list
>> USRP-users <at> lists.ettus.com
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>
> One more question. In order to getting started in RFNoC i have tried to
> connect by Network Mode.
> First of all i updated my SDimage to release 4 version. Second rebuilt and
> reinstall UHD enabling Network mode on E300. Third, set the device ip
> address to static 192.168.1.123 and finally launch network mode on the
> device (usrp_e3x0_network_mode; after doing that all RX-TX leds turned on).
> And when i run my flow graph (on my PC) y get an error:
>
> linux; GNU C++ version 4.8.4; Boost_105400; UHD_003.010.rfnoc-316-gb7546712
>
> -- Initializing core control...
> -- Performing register loopback test... pass
> Traceback (most recent call last):
> File "/home/ignazio/top_block.py", line 158, in <module>
> main()
> File "/home/ignazio/top_block.py", line 146, in main
> tb = top_block_cls()
> File "/home/ignazio/top_block.py", line 69, in __init__
> channels=range(1),
> File "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/__init__.py",
> line 122, in constructor_interceptor
> return old_constructor(*args)
> File "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/uhd_swig.py",
> line 2239, in make
> return _uhd_swig.usrp_source_make(*args)
> RuntimeError: RuntimeError: Expected FPGA compatibility number 255.x, but
> got 14.0:
> The FPGA build is not compatible with the host code build.
> Please run:
>
> "/usr/local/lib/uhd/utils/uhd_images_downloader.py"
This message is misleading in the E310 case.
For an E310 in network mode, what is important is the versions of uhd
must match. release-4 has uhd-3.9.2 installed, so you must use uhd-3.9.2
on the PC also.
Philip
>
>>>> Done
>
> After run uhd_images_downloader.py the error is the same.
>
> When i look for USRP devices the output is:
> ignazio@Heimdall:/usr/local/lib/uhd/utils$ uhd_find_devices
> linux; GNU C++ version 4.8.4; Boost_105400; UHD_003.010.rfnoc-316-gb7546712
>
> --------------------------------------------------
> -- UHD Device 0
> --------------------------------------------------
> Device Address:
> type: e3x0
> addr: 192.168.1.123
> name:
> serial: 30B0160
> product: 30674
>
> And, in the E310 terminal:
>
> root@ettus-e3xx-sg1:~# usrp_e3x0_network_mode
> linux; GNU C++ version 4.9.2; Boost_105700; UHD_003.009.002-0-unknown
>
> -- Loading FPGA image: /usr/share/uhd/images/usrp_e310_fpga.bit... done
> -- e300 run server on port 21756 for RX
> -- e300 socket accept on port 21756 for RX
> -- e300 run server on port 21762 for SENSOR
> -- e300 run server on port 21857 for TX
> -- e300 run server on port 21858 for CTRL
> -- e300 run server on port 21761 for I2C
> -- e300 run server on port 21856 for RX
> -- e300 socket accept on port 21857 for TX
> -- e300 run server on port 21757 for TX
> -- e300 socket accept on port 21757 for TX
> -- e300 socket accept on port 21858 for CTRL
> -- e300 run server on port 21758 for CTRL
> -- e300 socket accept on port 21758 for CTRL
> -- e300 socket accept on port 21761 for I2C
> -- e300 socket accept on port 21762 for SENSOR
> -- e300 run server on port 21760 for GREGS
> -- e300 socket accept on port 21760 for GREGS
> -- e300 socket accept on port 21856 for RX
> -- e300 run server on port 21759 for CODEC
> -- e300 socket accept on port 21759 for CODEC
>
>
> Thanks all
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
------------------------------
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