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Today's Topics:
1. Re: E310 (RFNoC not PC host) (Ignazio Finazzi)
2. RFNoC Polyphase Filterbank Channelizer / Synthesizer (Anselm Karl)
3. Re: LIBUSB error when connecting to multiple B210s
(Joshua Sendall)
4. Re: FPGA update (Neel Pandeya)
5. Re: X310 product code unknown EEPROM (Neel Pandeya)
----------------------------------------------------------------------
Message: 1
Date: Mon, 18 Apr 2016 07:56:12 +0000 (UTC)
From: Ignazio Finazzi <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] E310 (RFNoC not PC host)
Message-ID: <[email protected]>
Content-Type: text/plain; charset=us-ascii
Ignazio Finazzi via USRP-users <usrp-users@...> writes:
Solved problems. The UHD version in the SD image was 3.09 and in my host pc
was 3.10, downgrade host pc version and re-build GNU-radio and the system works.
Thanks all
------------------------------
Message: 2
Date: Mon, 18 Apr 2016 15:38:54 +0200
From: Anselm Karl <[email protected]>
To: [email protected]
Subject: [USRP-users] RFNoC Polyphase Filterbank Channelizer /
Synthesizer
Message-ID:
<cafokedjpy5w97u2lc_vgmxhz8mexdke40jkylfeccjkieax...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi all,
i just pushed a RFNoC Implementation of a Polyphase Filterbank Channelizer
and Synthesizer to github.
https://github.com/e33b1711/rfnoc_pp_channelizer
There are some issues left, but it works. Feel free to test it, use it,
change it and to give me feedback.
There is a bitfile for the X310 with a channelizer and a synthesizer with
16 subchannels. To add the blocks in your on image you can use my sources +
some synthesized checkpoints. For customizing the blocks (for example for
more subchannels) you'll need System Generator. The SysGen models are also
on github.
Something, that might be interesting to the Ettus People: I saw you are
working on a polyphase filterbank, that is not based on the Xilinx FIR
Compiler but completely hand written. First I did something similar,
because i thought the FIR Compiler can't provide a different impulse
response for each tdm channel. But meanwhile i learned it can. The option
was not very good to find in the FIR Compilers data sheet. Or is there a
completely other reason for handwriting the filter?
Cheers,
Anselm
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Message: 3
Date: Mon, 18 Apr 2016 15:46:22 +0200
From: Joshua Sendall <[email protected]>
To: Derek Kozel <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] LIBUSB error when connecting to multiple
B210s
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
Hi Derek,
Oh Sorry, I didn't see that the group was no longer CCed.
So for a single multi_usrp object the initialization code is:
//Create a usrp device cout << std::endl << boost::format("Creating the
usrp device with: %s...") % strUSRPArgs << endl; m_pUSRP =
uhd::usrp::multi_usrp::make(strUSRPArgs);
where strUSRPArgs is a std::string and equal to "serial=F459A3,serial=F5C1CC".
The code outputs:
Creating the usrp device with: serial=F459A3,serial=F5C1CC...-- Operating over
USB 3.-- Initialize CODEC control...-- Initialize Radio control...-- Performing
register loopback test... pass-- Performing register loopback test... pass--
Performing CODEC loopback test... pass-- Performing CODEC loopback test...
pass-- Asking for clock rate 32.000000 MHz-- Actually got clock rate 32.000000
MHz-- Performing timer loopback test... pass-- Performing timer loopback
test... pass
So to view the available channels we use:
std::cout << boost::format("Using Device: %s") %
m_pUSRP->get_pp_string() << std::endl;
which outputs:
Using Device: Single USRP: Device: B-Series Device Mboard 0: B210 RX
Channel: 0 RX DSP: 0 RX Dboard: A RX Subdev: FE-RX2 RX Channel: 1
RX DSP: 1 RX Dboard: A RX Subdev: FE-RX1 TX Channel: 0 TX DSP: 0
TX Dboard: A TX Subdev: FE-TX2 TX Channel: 1 TX DSP: 1 TX Dboard: A
TX Subdev: FE-TX1
This output is why I assumed only one B210 board was initialized and available
to use. So to remedy it I split the args into a std::vector<std::string> and
the initialization becomes:
//Create usrp devices m_pUSRP.clear(); for (size_t idx = 0;
idx < strUSRPArgs.size(); idx++) { cout << std::endl <<
boost::format("Creating the usrp device with: %s...") % strUSRPArgs[idx] <<
endl;
m_pUSRP.push_back(uhd::usrp::multi_usrp::make(strUSRPArgs[idx])); }
While in the second loop, during the execution of the second make push_back,
the libusb error occurs.
Date: Sun, 17 Apr 2016 11:22:29 -0700
Subject: RE: [USRP-users] LIBUSB error when connecting to multiple B210s
From: [email protected]
To: [email protected]
Hi Josh,
You can certainly get all the RX and TX channels in a single device. Can you
share your initialization line with me as well as how your are accessing the
channels?
Also do you mind if we return this conversation to the mailing list so others
can benefit as well?
Derek
On Apr 17, 2016 10:31 AM, <[email protected]> wrote:
Hi Derek,
Thanks, I originally tried that but for some reason if I initialize a
multi_usrp with the args as "serial=xxxxx,serial=yyyyy" it only creates
channels for the first board. So the method of using multiple multi_usrp
objects was really a work around.
If you can create multiple b210 in a single multi_usrp, however, that would
indicate that my initialization procedure is flawed, and I must go change it
up. So please let me know if you have any success with either procedure, abd
thanks again for the help.
Kind regards,
Josh
Sent from Outlook Mobile
From: Derek Kozel
Sent: Sunday 17 April, 18:43
Subject: RE: [USRP-users] LIBUSB error when connecting to multiple B210s
To: Joshua Sendall
Hi Josh,
I'll look into this on Monday and let you know if I see the same behavior and
if so what a fix would be. Another option is to have both B210s in the same
multi_usrp object.
Regards,
Derek
On Apr 16, 2016 11:56 PM, "Joshua Sendall" <[email protected]> wrote:
Hi Derek,
I forgot to add that the error gets repeatedly printed until the program
crashes. It first appeared in version 003.009.000, i.e. it works fine on
003.008.005. Unfortunately version 3.8.5 does not yet have the analogue filters
fully implemented.
Kind regards,
Josh
From: [email protected]
To: [email protected]
Subject: RE: [USRP-users] LIBUSB error when connecting to multiple B210s
Date: Sun, 17 Apr 2016 07:12:38 +0200
Hi Derek,
I am creating the two USRP objects sequentially in the same process (literally
running in a loop). I attached a screen shot of the console output.
Kind regards,
Josh
Date: Sat, 16 Apr 2016 21:35:23 -0700
Subject: Re: [USRP-users] LIBUSB error when connecting to multiple B210s
From: [email protected]
To: [email protected]
CC: [email protected]
Hello Joshua,
Are you creating the two multi USRP objects in the same process? Can you attach
or paste the UHD output here?
Thanks,
Derek
On Apr 16, 2016 11:42 AM, "Joshua Sendall via USRP-users"
<[email protected]> wrote:
Hi all,
I have encountered an issue after updating to the latest firmware version
(003.009.003 on Windows 10) on the B210s. The issue I have is when creating a
second multi_usrp instance a "LIBUSB_ERROR_CODE -1" error gets repeatedly
printed after printing "Operating over USB 3" to the console.
Has anyone seen such an error or know what might solve it?
Kind regards,
Joshua Sendall
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Message: 4
Date: Mon, 18 Apr 2016 08:08:18 -0700
From: Neel Pandeya <[email protected]>
To: Diyar Muhammed <[email protected]>
Cc: usrp-users <[email protected]>
Subject: Re: [USRP-users] FPGA update
Message-ID:
<CACaXmv-cajbrf1yAkmiTMs3i=YhHHnxh-4yO0uhKS4=73pt...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hello Diyar:
It sounds like "uhd_images_downloader". Either invoke it with the full
pathname, or add its path to your PATH environment variable.
Also you will probably need to run it as root, with "sudo".
--Neel
On 23 March 2016 at 12:19, Diyar Muhammed via USRP-users <
[email protected]> wrote:
> Dear All,
> I have got new usrp x310 with UBX160 daughter board, I assembled the usrp,
> but when I run the uhd_usrp_probe --args addr=192.168.10.2 there is a UHD
> Warning:
> *X300 unknown product code in EEPROM:30818*
> *Error: RuntimeError: Expected firmware compatibility number 3.0, but got
> 4.0:*
> *The firmware build is not compatible with the host code build.*
> *Please run:*
> * "/usr/local/lib/uhd/utils/uhd_images_downloader.py"*
>
> I found from ettus website how I can download and update image (
> http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_1gige) but when
> I run uhd_image_loader --args="type=x300,addr=192.168.10.2,fpga=HGS", I
> got from terminal uhd_image_loader: command not found.
> I need advace, about this problem:
>
> *uhd_image_loader: command not found.*
>
> Regards,
> Diyar Muhammed
> Ministry of Higher Education and Scientific Research
> Duty: Network Administration and Design
> Website: www.mhe-krg.org
> Cell Phone: 009647504690060
> Office Phone: 00964662554683
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 5
Date: Mon, 18 Apr 2016 08:42:51 -0700
From: Neel Pandeya <[email protected]>
To: Mhe <[email protected]>
Cc: "Marcus D. Leech" <[email protected]>,
"[email protected]" <[email protected]>
Subject: Re: [USRP-users] X310 product code unknown EEPROM
Message-ID:
<CACaXmv8UjNQ6Rt4rue=wqbwfe1papdzbbyp_bh+uucutrz3...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
It depends on how you installed UHD.
You can do a git checkout of 3.9.2, and re-build and re-install.
I would suggest using specifically 3.9.2.
--Neel
On 24 March 2016 at 01:02, Mhe via USRP-users <[email protected]>
wrote:
> Dear Marcus,
> Many thank for your advice,
> How I can upgrade UHD?
> Regards,
> Diyar Muhammed
> M: 009647504690060
>
> > On Mar 24, 2016, at 12:50 AM, Marcus D. Leech <[email protected]> wrote:
> >
> >> On 03/23/2016 06:09 PM, Diyar Muhammed via USRP-users wrote:
> >> Dear All,
> >> I assembled usrp x310, and I had a warning, so I downloaded FPGA image
> and then I have upgraded FPGA by using the command: usrp_x3xx_fpga_burner
> --addr=192.168.10.2
> --fpga-path=/usr/local/share/uhd/images/usrp_x310_fpga_HGS.bit.
> >> after that the usrp x310 is able to find daughter board, but still I
> have a UHD warning as shown in the below, as shown below:
> >>
> >> mint@mint ~ $ uhd_usrp_probe 192.168.10.2
> >> linux; GNU C++ version 4.8.2; Boost_105400;
> UHD_003.008.001-105-g91ae742f
> > You have a newer X310 hardware version that isn't supported by that
> very-old version of UHD. Newer X310s *CANNOT* be supported by
> > older UHD due to hardware changes that were made.
> >
> > Upgrade to 3.9.2 or the just-released 3.9.3 UHD version.
> >
> >
> >>
> >> UHD Warning:
> >> X300 unknown product code in EEPROM: 30818
> >>
> >> UHD Warning:
> >> X300 unknown product code in EEPROM: 30818
> >>
> >> UHD Warning:
> >> X300 unknown product code in EEPROM: 30818
> >>
> >> UHD Warning:
> >> X300 unknown product code in EEPROM: 30818
> >> -- X300 initialization sequence...
> >> -- Determining maximum frame size... 1472 bytes.
> >> -- Setup basic communication...
> >> -- Loading values from EEPROM...
> >>
> >> UHD Warning:
> >> X300 unknown product code in EEPROM: 30818
> >> -- Setup RF frontend clocking...
> >> -- Radio 1x clock:200
> >> -- Initialize Radio control...
> >> -- Performing register loopback test... pass
> >> -- Performing register loopback test... pass
> >> -- Initializing clock and time using internal sources... done
> >> _____________________________________________________
> >> /
> >> | Device: X-Series Device
> >> | _____________________________________________________
> >> | /
> >> | | Mboard: X300?
> >> | | revision: 8
> >> | | product: 30818
> >> | | mac-addr0: 00:80:2f:23:7b:6f
> >> | | mac-addr1: 00:80:2f:23:7b:70
> >> | | gateway: 192.168.10.1
> >> | | ip-addr0: 192.168.10.2
> >> | | subnet0: 255.255.255.0
> >> | | ip-addr1: 192.168.20.2
> >> | | subnet1: 255.255.255.0
> >> | | ip-addr2: 192.168.30.2
> >> | | subnet2: 255.255.255.0
> >> | | ip-addr3: 192.168.40.2
> >> | | subnet3: 255.255.255.0
> >> | | serial: 30C0991
> >> | | FW Version: 3.0
> >> | | FPGA Version: 9.0
> >> | |
> >> | | Time sources: internal, external, gpsdo
> >> | | Clock sources: internal, external, gpsdo
> >> | | Sensors: ref_locked
> >> | | _____________________________________________________
> >> | | /
> >> | | | RX DSP: 0
> >> | | | Freq range: -100.000 to 100.000 MHz
> >> | | _____________________________________________________
> >> | | /
> >> | | | RX DSP: 1
> >> | | | Freq range: -100.000 to 100.000 MHz
> >> | | _____________________________________________________
> >> | | /
> >> | | | RX Dboard: A
> >> | | | ID: UBX-160 v1 (0x007a)
> >> | | | Serial: 30C2AAB
> >> | | | _____________________________________________________
> >> | | | /
> >> | | | | RX Frontend: 0
> >> | | | | Name: UBX RX
> >> | | | | Antennas: TX/RX, RX2, CAL
> >> | | | | Sensors: lo_locked
> >> | | | | Freq range: 10.000 to 6000.000 MHz
> >> | | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
> >> | | | | Connection Type: IQ
> >> | | | | Uses LO offset: No
> >> | | | _____________________________________________________
> >> | | | /
> >> | | | | RX Codec: A
> >> | | | | Name: ads62p48
> >> | | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
> >> | | _____________________________________________________
> >> | | /
> >> | | | RX Dboard: B
> >> | | | ID: UBX-160 v1 (0x007a)
> >> | | | Serial: 30C2A33
> >> | | | _____________________________________________________
> >> | | | /
> >> | | | | RX Frontend: 0
> >> | | | | Name: UBX RX
> >> | | | | Antennas: TX/RX, RX2, CAL
> >> | | | | Sensors: lo_locked
> >> | | | | Freq range: 10.000 to 6000.000 MHz
> >> | | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
> >> | | | | Connection Type: IQ
> >> | | | | Uses LO offset: No
> >> | | | _____________________________________________________
> >> | | | /
> >> | | | | RX Codec: B
> >> | | | | Name: ads62p48
> >> | | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
> >> | | _____________________________________________________
> >> | | /
> >> | | | TX DSP: 0
> >> | | | Freq range: -100.000 to 100.000 MHz
> >> | | _____________________________________________________
> >> | | /
> >> | | | TX DSP: 1
> >> | | | Freq range: -100.000 to 100.000 MHz
> >> | | _____________________________________________________
> >> | | /
> >> | | | TX Dboard: A
> >> | | | ID: UBX-160 v1 (0x0079)
> >> | | | Serial: 30C2AAB
> >> | | | _____________________________________________________
> >> | | | /
> >> | | | | TX Frontend: 0
> >> | | | | Name: UBX TX
> >> | | | | Antennas: TX/RX, CAL
> >> | | | | Sensors: lo_locked
> >> | | | | Freq range: 10.000 to 6000.000 MHz
> >> | | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
> >> | | | | Connection Type: QI
> >> | | | | Uses LO offset: No
> >> | | | _____________________________________________________
> >> | | | /
> >> | | | | TX Codec: A
> >> | | | | Name: ad9146
> >> | | | | Gain Elements: None
> >> | | _____________________________________________________
> >> | | /
> >> | | | TX Dboard: B
> >> | | | ID: UBX-160 v1 (0x0079)
> >> | | | Serial: 30C2A33
> >> | | | _____________________________________________________
> >> | | | /
> >> | | | | TX Frontend: 0
> >> | | | | Name: UBX TX
> >> | | | | Antennas: TX/RX, CAL
> >> | | | | Sensors: lo_locked
> >> | | | | Freq range: 10.000 to 6000.000 MHz
> >> | | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
> >> | | | | Connection Type: QI
> >> | | | | Uses LO offset: No
> >> | | | _____________________________________________________
> >> | | | /
> >> | | | | TX Codec: B
> >> | | | | Name: ad9146
> >> | | | | Gain Elements: None
> >>
> >> mint@mint ~ $
> >>
> >> What I have to do to sort out that?
> >> in advance many thanks.
> >
>
> _______________________________________________
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> [email protected]
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