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Today's Topics:
1. Loopback of RFNoC version (Zhihong Luo)
2. External reference for USRP2 (jj08)
3. Re: X310 UBX Tx issues ([email protected])
4. Re: External reference for USRP2 (James Humphries)
5. Re: External reference for USRP2 (jj08)
6. Re: External reference for USRP2 (Martin Braun)
7. Re: X310 UBX Tx issues ([email protected])
8. Tomorrow! Cyberspectrum: Software Defined Radio Meetup (Wed
20th April) 6:30pm (Balint Seeber)
9. building a MIMO system without PPS signal (Yang Liu)
10. Re: building a MIMO system without PPS signal (Marcus D. Leech)
11. Re: Loopback of RFNoC version (Marcus D. Leech)
12. Re: External reference for USRP2 (jj08)
13. Re: building a MIMO system without PPS signal (Marcus D. Leech)
14. Re: building a MIMO system without PPS signal (Ian Buckley)
15. Re: E310 : Interfacing ZynQ 7020 with AD 9361 RFIC and Filter
Banks (BHUSHAN PAWAR)
16. Re: E310 : Interfacing ZynQ 7020 with AD 9361 RFIC and Filter
Banks (BHUSHAN PAWAR)
17. Re: building a MIMO system without PPS signal (Marcus M?ller)
18. b200mini: using GPIO pin for PPS reference (Sean Nowlan)
19. Re: E310 : Interfacing ZynQ 7020 with AD 9361 RFIC and Filter
Banks (Jonathon Pendlum)
----------------------------------------------------------------------
Message: 1
Date: Tue, 19 Apr 2016 12:30:01 -0400
From: Zhihong Luo <[email protected]>
To: Zhihong Luo via USRP-users <[email protected]>
Subject: [USRP-users] Loopback of RFNoC version
Message-ID:
<CAH4wXLr0nWoBJY=0qeiqc8lulusenpdy1xuhus0tsfcxpsd...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi all,
Is it right that for RFNoC version,one Radio block can only serve as either
RX or TX, so that we can not do loop back on one motherboard? I used to be
able to do it on the ordinary version.
Thanks,
Zhihong
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------------------------------
Message: 2
Date: Tue, 19 Apr 2016 10:06:55 -0700
From: "jj08" <[email protected]>
To: [email protected]
Subject: [USRP-users] External reference for USRP2
Message-ID: <1062478411000000009736706@www>
Content-Type: text/plain; charset="utf-8"
Hello Experts,
I am brand new to USRP.
I have connected analog signal generator's sine wave output (999.999 MHz,
-30dBm) to the USRP2 (Rx2).
A Rb 10 MHz freq. standard provides reference signal to the signal generator
as well as to the USRP2.
I have set the carrier frequency of the radio at 1GHz.
I am trying to see the output of rx_stream.
I expected a 1kHz sine wave signal, but I just get a flat line. I want to see
a sine curve, but have no idea what other parameters do I need to provide and
where and how.
Here are the values I have set:
//----------------------------------------------------- //setup the program
options po::options_description desc("Allowed options");
("args", po::value<std::string>(&args)->default_value(""),
"multi uhd device address args") ("type",
po::value<std::string>(&type)->default_value("short"), "sample
type: double, float, or short") ("nsamps",
po::value<size_t>(&total_num_samps)->default_value(0), "total number of
samples to receive") ("duration",
po::value<double>(&total_time)->default_value(0), "total number of seconds
to receive") ("spb",
po::value<size_t>(&spb)->default_value(10000), "samples per buffer")
("rate", po::value<double>(&rate)->default_value(10e6), "rate of
incoming samples") ("freq",
po::value<double>(&freq)->default_value(1e9), "RF center frequency in
Hz") ("gain", po::value<double>(&gain), &q
uot;gain for the RF chain") ("ant",
po::value<std::string>(&ant)->default_value("RX2"), "antenna
selection") ("subdev", po::value<std::string>(&subdev),
"subdevice specification") ("bw", po::value<double>(&bw),
"analog frontend filter bandwidth in Hz") ("ref",
po::value<std::string>(&ref)->default_value("external"),
"reference source (internal, external, mimo)") ("wirefmt",
po::value<std::string>(&wirefmt)->default_value("sc16"), "wire
format (sc8 or sc16) ("setup",
po::value<double>(&setup_time)->default_value(1.0), "seconds of setup
time") ("progress", "periodically display short-term
bandwidth") ("stats", "show average bandwidth on
exit") ("sizemap", "track packet size and display breakdown
on exit") ("null", "run without writing to file")
("continu
e", "don't abort on a bad packet") ("skip-lo",
"skip checking LO lock status") ("int-n", "tune USRP
with integer-N tuning") ; //----------------------------------------------
When I set reference source to "internal", and with all other
setting as it is, I *do* get a desired output, a nice looking sine wave.
What should I be doing to get a sine wave while using an external ref.?
Any pointers would be highly appreciated.
Thank you very much for your time and guidance.
Cheers!
-------------------------
Online Storage & Sharing, Online Backup, FTP / Email Server Hosting and More.
Drive Headquarters. Top quality services designed for business! Sign up free
at: www.DriveHQ.com
.
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------------------------------
Message: 3
Date: Tue, 19 Apr 2016 17:15:37 +0000 (UTC)
From: [email protected]
To: Marcus M?ller <[email protected]>, Neel Pandeya
<[email protected]>
Cc: usrp-users <[email protected]>
Subject: Re: [USRP-users] X310 UBX Tx issues
Message-ID:
<[email protected]>
Content-Type: text/plain; charset="utf-8"
Nothing yet.
Neel, listed below, UHD 3.9.2...
I can get you a probe output in a bit...
----- Original Message -----
From: "Marcus M?ller via USRP-users" <[email protected]>
To: "usrp-users" <[email protected]>
Sent: Tuesday, April 19, 2016 11:39:59 AM
Subject: Re: [USRP-users] X310 UBX Tx issues
Hi Tilla,
I totally got lost in the discussions involving you, of which some were
off-list; has this been addressed?
Best regards,
Marcus
On 04/04/2016 05:59 PM, tilla--- via USRP-users wrote:
Platform:
Win 7 64 bit
UHD 3.9.2
Visual Studio 2015 Update 1
X310 with UBX-160
10Gb interface
I am porting my hardware platform from WBX-120 cards over to UBX-160.
There are some strange things going on with UBX-160.
Looking at the output signal on a spectrum analyzer zero span 1 MHz BW at
center frequency, the noise floor is about -75 dbm.
executing the command tx_waveforms --args addr=192.168.40.2 --rate 10000000
--freq 300000000
When the app starts, signal level goes to about -70 dbm for 1 second, then -48
dbm for about 2 seconds, then to -15 dbm for the remainder of the application
execution. Upon control-c of the application to halt, a signal is still being
transmitted by the card at -53 dbm.
When run on a WBX-120, none of these startup or shutdown artifacts are present.
Seems to be present on all frequencies at varying amplitudes.
I have tried this on multiple X310s and multiple UBX cards, all exhibit the
same performance.
Is this something you guys are aware of?
Thanks,
_______________________________________________
USRP-users mailing list [email protected]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
_______________________________________________
USRP-users mailing list
[email protected]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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------------------------------
Message: 4
Date: Tue, 19 Apr 2016 13:48:09 -0400
From: James Humphries <[email protected]>
To: jj08 <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] External reference for USRP2
Message-ID:
<CAEwGFhXz+w=xkegu4gkzqqdevqvho1y7njh+en-ye5kedgs...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hello,
Is this a program you wrote or are you using one of the example programs?
Which version of UHD are you using?
What are the specs of your 10MHz reference? Have you verified its operation?
-Trip
On Tue, Apr 19, 2016 at 1:06 PM, jj08 via USRP-users <
[email protected]> wrote:
> Hello Experts,
>
> I am brand new to USRP.
>
> I have connected analog signal generator's sine wave output (999.999 MHz,
> -30dBm) to the USRP2 (Rx2).
>
> A Rb 10 MHz freq. standard provides reference signal to the signal
> generator as well as to the USRP2.
>
> I have set the carrier frequency of the radio at 1GHz.
>
> I am trying to see the output of rx_stream.
>
> I expected a 1kHz sine wave signal, but I just get a flat line. I want to
> see a sine curve, but have no idea what other parameters do I need to
> provide and where and how.
>
> Here are the values I have set:
>
> //-----------------------------------------------------
>
> //setup the program options
> po::options_description desc("Allowed options");
> ("args", po::value(&args)->default_value(""), "multi uhd device address
> args")
> ("type", po::value(&type)->default_value("short"), "sample type: double,
> float, or short")
> ("nsamps", po::value(&total_num_samps)->default_value(0), "total number of
> samples to receive")
> ("duration", po::value(&total_time)->default_value(0), "total number of
> seconds to receive")
> ("spb", po::value(&spb)->default_value(10000), "samples per buffer")
> ("rate", po::value(&rate)->default_value(10e6), "rate of incoming samples")
> ("freq", po::value(&freq)->default_value(1e9), "RF center frequency in Hz")
> ("gain", po::value(&gain), "gain for the RF chain")
> ("ant", po::value(&ant)->default_value("RX2"), "antenna selection")
> ("subdev", po::value(&subdev), "subdevice specification")
> ("bw", po::value(&bw), "analog frontend filter bandwidth in Hz")
> ("ref", po::value(&ref)->default_value("external"), "reference source
> (internal, external, mimo)")
> ("wirefmt", po::value(&wirefmt)->default_value("sc16"), "wire format (sc8
> or sc16)
> ("setup", po::value(&setup_time)->default_value(1.0), "seconds of setup
> time")
> ("progress", "periodically display short-term bandwidth")
> ("stats", "show average bandwidth on exit")
> ("sizemap", "track packet size and display breakdown on exit")
> ("null", "run without writing to file")
> ("continue", "don't abort on a bad packet")
> ("skip-lo", "skip checking LO lock status")
> ("int-n", "tune USRP with integer-N tuning")
> ;
> //----------------------------------------------
>
>
> When I set reference source to "internal", and with all other setting as
> it is, I *do* get a desired output, a nice looking sine wave.
>
> What should I be doing to get a sine wave while using an external ref.?
>
> Any pointers would be highly appreciated.
>
> Thank you very much for your time and guidance.
>
> Cheers!
>
> -------------------------
> Online Storage & Sharing, Online Backup, FTP / Email Server Hosting and
> More.
> Drive Headquarters. Top quality services designed for business!
> Sign up free at: www.DriveHQ.com
> <http://www.drivehq.com/?refID=178949&refEmails=&refCode=>.
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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------------------------------
Message: 5
Date: Tue, 19 Apr 2016 11:18:58 -0700
From: "jj08" <[email protected]>
To: [email protected], [email protected]
Cc: [email protected]
Subject: Re: [USRP-users] External reference for USRP2
Message-ID: <1062531071000000009736706@www>
Content-Type: text/plain; charset="utf-8"
Thank you for your message.
No, I did not write this program. Someone gave it to me for test/further
development.
I found a page, some parts of the code are similar or exact same.
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2014-August/010414.html
About the 10 MHz reference, I don't have the spec with me right now, when I go
back to work, I will find out and post it.
Assuming the reference is ok, what else could I investigate?
The UHD driver is uhd_003.009.003-release_Win64_VS2015.exe
--From: [email protected]
--To: [email protected]
--CC: [email protected]
--Date: 4/19/2016 10:48:30 AM --Subject: Re: [USRP-users] External reference
for USRP2 Hello, Is this a program you wrote or are you using one of the
example programs? Which version of UHD are you using? What are the specs of
your 10MHz reference? Have you verified its operation? -Trip
On Tue, Apr 19, 2016 at 1:06 PM, jj08 via USRP-users <<a target="_blank"
href="mailto:[email protected]";>[email protected]>
wrote:
Hello Experts,
I am brand new to USRP.
I have connected analog signal generator's sine wave output (999.999 MHz,
-30dBm) to the USRP2 (Rx2).
A Rb 10 MHz freq. standard provides reference signal to the signal generator
as well as to the USRP2.
I have set the carrier frequency of the radio at 1GHz.
I am trying to see the output of rx_stream.
I expected a 1kHz sine wave signal, but I just get a flat line. I want to see
a sine curve, but have no idea what other parameters do I need to provide and
where and how.
Here are the values I have set:
//----------------------------------------------------- //setup the program
options po::options_description desc("Allowed options");
("args", po::value(&args)->default_value(""), "multi
uhd device address args") ("type",
po::value(&type)->default_value("short"), "sample type: double,
float, or short") ("nsamps",
po::value(&total_num_samps)->default_value(0), "total number of samples to
receive") ("duration", po::value(&total_time)->default_value(0),
"total number of seconds to receive") ("spb",
po::value(&spb)->default_value(10000), "samples per buffer")
("rate", po::value(&rate)->default_value(10e6), "rate of
incoming samples") ("freq",
po::value(&freq)->default_value(1e9), "RF center frequency in Hz")
("gain", po::value(&gain), "gain for the RF chain")
("ant", po::value(&ant)->defaul
t_value("RX2"), "antenna selection") ("subdev",
po::value(&subdev), "subdevice specification") ("bw",
po::value(&bw), "analog frontend filter bandwidth in Hz")
("ref", po::value(&ref)->default_value("external"),
"reference source (internal, external, mimo)") ("wirefmt",
po::value(&wirefmt)->default_value("sc16"), "wire format (sc8 or
sc16) ("setup", po::value(&setup_time)->default_value(1.0),
"seconds of setup time") ("progress", "periodically
display short-term bandwidth") ("stats", "show average
bandwidth on exit") ("sizemap", "track packet size and
display breakdown on exit") ("null", "run without writing
to file") ("continue", "don't abort on a bad packet")
("skip-lo", "skip checking LO lock status")
("int-n", "tu
ne USRP with integer-N tuning") ;
//----------------------------------------------
When I set reference source to "internal", and with all other
setting as it is, I *do* get a desired output, a nice looking sine wave.
What should I be doing to get a sine wave while using an external ref.?
Any pointers would be highly appreciated.
Thank you very much for your time and guidance.
Cheers!
-------------------------
Online Storage & Sharing, Online Backup, FTP / Email Server Hosting and More.
Drive Headquarters. Top quality services designed for business! Sign up free
at: www.DriveHQ.com.
_______________________________________________
USRP-users mailing list [email protected]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
-------------------------
Online Storage & Sharing, Online Backup, FTP / Email Server Hosting and More.
Drive Headquarters. Top quality services designed for business! Sign up free
at: www.DriveHQ.com
.
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------------------------------
Message: 6
Date: Tue, 19 Apr 2016 12:14:09 -0700
From: Martin Braun <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] External reference for USRP2
Message-ID: <[email protected]>
Content-Type: text/plain; charset=windows-1252
Have you tried setting a larger offset (e.g. 1 MHz or even larger)? At
10 Msps you need 1e4 samples to see one single wave cycle, and it seems
you're plotting a few hundred.
Also, there's tools like GNU Radio that make this kind of thing much,
much easier to test.
Cheers,
M
On 04/19/2016 10:06 AM, jj08 via USRP-users wrote:
> Hello Experts,
>
> I am brand new to USRP.
>
> I have connected analog signal generator's sine wave output (999.999
> MHz, -30dBm) to the USRP2 (Rx2).
>
> A Rb 10 MHz freq. standard provides reference signal to the signal
> generator as well as to the USRP2.
>
> I have set the carrier frequency of the radio at 1GHz.
>
> I am trying to see the output of rx_stream.
>
> I expected a 1kHz sine wave signal, but I just get a flat line. I want
> to see a sine curve, but have no idea what other parameters do I need
> to provide and where and how.
>
> Here are the values I have set:
>
> //-----------------------------------------------------
>
> //setup the program options
> po::options_description desc("Allowed options");
> ("args", po::value(&args)->default_value(""), "multi uhd device address
> args") ("type",
> po::value(&type)->default_value("short"), "sample type: double, float,
> or short") ("nsamps", po::value(&total_num_samps)->default_value(0),
> "total number of samples to receive") ("duration",
> po::value(&total_time)->default_value(0), "total number of seconds to
> receive") ("spb", po::value(&spb)->default_value(10000), "samples per
> buffer") ("rate", po::value(&rate)->default_value(10e6), "rate of
> incoming samples") ("freq", po::value(&freq)->default_value(1e9), "RF
> center frequency in Hz") ("gain", po::value(&gain), "gain for the RF
> chain") ("ant", po::value(&ant)->default_value("RX2"), "antenna
> selection") ("subdev", po::value(&subdev), "subdevice specification")
> ("bw", po::value(&bw), "analog frontend filter bandwidth in Hz") ("ref",
> po::value(&ref)->default_value("external"), "reference source (internal,
> external, mimo)") ("wirefmt",
> po::value(&wirefmt)->default_value("sc16"), "wire format (sc8 or sc16)
> ("setup", po::value(&setup_time)->default_value(1.0), "seconds of setup
> time") ("progress", "periodically display short-term bandwidth")
> ("stats", "show average bandwidth on exit") ("sizemap", "track packet
> size and display breakdown on exit") ("null", "run without writing to
> file") ("continue", "don't abort on a bad packet") ("skip-lo", "skip
> checking LO lock status") ("int-n", "tune USRP with integer-N tuning") ;
> //----------------------------------------------
>
> When I set reference source to "internal", and with all other setting as
> it is, I *do* get a desired output, a nice looking sine wave.
>
> What should I be doing to get a sine wave while using an external ref.?
>
> Any pointers would be highly appreciated.
>
> Thank you very much for your time and guidance.
>
> Cheers!
>
>
> -------------------------
> Online Storage & Sharing, Online Backup, FTP / Email Server Hosting and
> More.
> Drive Headquarters. Top quality services designed for business!
> Sign up free at: www.DriveHQ.com
> <http://www.drivehq.com/?refID=178949&refEmails=&refCode=>.
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
------------------------------
Message: 7
Date: Tue, 19 Apr 2016 21:10:24 +0000 (UTC)
From: [email protected]
To: [email protected]
Cc: Marcus M?ller <[email protected]>, Neel Pandeya
<[email protected]>, usrp-users <[email protected]>
Subject: Re: [USRP-users] X310 UBX Tx issues
Message-ID:
<[email protected]>
Content-Type: text/plain; charset="utf-8"
Probe output attached...
?
As a bonus, on page 3, there is a spectrum analyzer screen shot of the output
of uhd_usrp_probe...
?
Yes, there is rf output similar to described within tx_waveforms original issue
to start this thread.
?
The lowest signal level is the noise floor, the second level is output during
some of the startup of?uhd_usrp_probe, the third level is output forever, even
after the?uhd_usrp_probe application has exited...
----- Original Message -----
From: "tilla--- via USRP-users" <[email protected]>
To: "Marcus M?ller" <[email protected]>, "Neel Pandeya"
<[email protected]>
Cc: "usrp-users" <[email protected]>
Sent: Tuesday, April 19, 2016 1:15:37 PM
Subject: Re: [USRP-users] X310 UBX Tx issues
Nothing yet.
Neel, listed below, UHD 3.9.2...
I can get you a probe output in a bit...
----- Original Message -----
From: "Marcus M?ller via USRP-users" <[email protected]>
To: "usrp-users" <[email protected]>
Sent: Tuesday, April 19, 2016 11:39:59 AM
Subject: Re: [USRP-users] X310 UBX Tx issues
Hi Tilla,
I totally got lost in the discussions involving you, of which some were
off-list; has this been addressed?
Best regards,
Marcus
On 04/04/2016 05:59 PM, tilla--- via USRP-users wrote:
Platform:
??? Win 7 64 bit
??? UHD 3.9.2
??? Visual Studio 2015 Update 1
??? X310 with UBX-160
??? 10Gb interface
?
I am porting my hardware platform from WBX-120 cards over to UBX-160.
?
There are some strange things going on with UBX-160.
?
Looking at the output signal on a spectrum analyzer zero span 1 MHz BW at
center frequency, the noise floor is about -75 dbm.
?
executing the command tx_waveforms --args addr=192.168.40.2 --rate 10000000
--freq 300000000
?
When the app starts, signal level goes to about -70 dbm for 1 second, then -48
dbm for about 2 seconds, then to -15 dbm?for the remainder of the application
execution.? Upon control-c of the application to halt, a signal is still being
transmitted by the card at -53 dbm.
?
When run on a WBX-120, none of these startup or shutdown artifacts are present.
?
Seems to be present on all frequencies at varying amplitudes.
?
I have tried this on multiple X310s and multiple UBX cards, all exhibit the
same performance.
?
Is this something you guys are aware of?
?
Thanks,
?
_______________________________________________
USRP-users mailing list [email protected]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
_______________________________________________
USRP-users mailing list
[email protected]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
_______________________________________________
USRP-users mailing list
[email protected]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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------------------------------
Message: 8
Date: Tue, 19 Apr 2016 16:49:48 -0700
From: Balint Seeber <[email protected]>
To: [email protected], [email protected]
Subject: [USRP-users] Tomorrow! Cyberspectrum: Software Defined Radio
Meetup (Wed 20th April) 6:30pm
Message-ID:
<CAD39kUxM3wFCGdBK7hn=p0j8tyvZVoCWBQ=q0+q61++e8ea...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Dear all,
Announcing the fifteenth Cyberspectrum meetup tomorrow, which will be held
in the South Bay!
Come along at 6:30pm for a 7pm sharp kickoff, and for those unable to
attend please join the live stream like last time:
https://www.youtube.com/watch?v=u8CYptnVv3Y
There's also IRC: #cyberspectrum on Freenode, and updates on Twitter
<https://twitter.com/spenchdotnet>.
Full details, including the speaker lineup/topics, are here:
http://www.meetup.com/Cyberspectrum/events/228537070/
On the agenda:
- "GNU Radio Update" (Martin Braun <https://twitter.com/braun_noise>)
- "An Audible Waterfall Plot" (Kevin Reid
<https://twitter.com/switchborg>)
- "Adding Dual 10 Gigabit Ethernet Capability to the USRP X300" (Paul
David <https://twitter.com/daulpavid>)
- (And, if there's time, some FMCW RADAR and/or spot jamming with GNU
Radio!)
If you're not familiar with Cyberspectrum: "The Bay Area SDR Meetup will
serve as a forum to exchange knowledge and ideas related to Software
Defined Radio (the software and hardware), and generally aim to get people
excited about all the applications that can be realised with the
technology. At each meetup, attendees will have the opportunity to present
their work/ideas to the group. Engineers, enthusiasts, hobbyists and people
of all experience levels are welcome, no matter what your software/hardware
background."
As always, if you would like to present at a future event about a project
you're working on, or something interesting you've discovered, please get
in touch!
Hope to see you there,
Balint
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------------------------------
Message: 9
Date: Tue, 19 Apr 2016 19:43:39 -0400
From: Yang Liu <[email protected]>
To: [email protected]
Subject: [USRP-users] building a MIMO system without PPS signal
Message-ID:
<CAD4vFMG2x70jTddvo51WB6iWw5dxE8MmT4=put2ee8bwupv...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Dear all,
Now I am trying to build a 2x2 MIMO system using 4 USRP N210s, and external
10MHz clock is used for frequency synchronization. However, PPS signal is
not available.
the setup is: each USRP is connected to the PC directly via ethernet cable
and thus, all 4 USRPs (2 as transmitters, 2 as receivers) are controlled by
the same host computer. 2 transmitting USRPs are synchronized by one 10MHz
clock, and 2 receiving USRPs are synchronized by another 10MHz clock.
In the beginning, I thought that our application doesn't require time
precision on every node, so frequency synchronization suffices. However,
the experiment acted poorly. The bit error rate at the receiver side was
very large. I thought it should be the problem with time synchronization
(Since the code I had works properly when the USRPs are synchronizied by
MIMO cables), so I followed some suggestions online to achieve time
synchronization at TX/RX:
https://www.ruby-forum.com/topic/4409521
http://files.ettus.com/manual/page_sync.html
here is the code for USRP N210 configuration at the transmitter side
(configuration at RX is very similar):
#################
transmitter
#################
self.usink0=uhd.usrp_sink(device_addr="addr0=192.168.10.2",
io_type=uhd.io_type.COMPLEX_FLOAT32, num_channels=1)
self.usink1=uhd.usrp_sink(device_addr="addr0=192.168.10.4",
io_type=uhd.io_type.COMPLEX_FLOAT32, num_channels=1)
self.usink0.set_clock_source("external")
self.usink1.set_clock_source("external")
self.usink0.set_time_now(uhd.time_spec_t(time.time())) #set the time
registers immediately
self.usink1.set_time_now(uhd.time_spec_t(time.time()))
self.usink0.set_samp_rate(self.samp_rate)
self.usink1.set_samp_rate(self.samp_rate)
self.usink0.set_gain(self.gain)
self.usink1.set_gain(self.gain)
self.usink0.set_antenna(self.antenna)
self.usink1.set_antenna(self.antenna)
future=time.time()+0.5
self.usink0.set_command_time(uhd.time_spec_t(future))
self.usink1.set_command_time(uhd.time_spec_t(future))
self.usink0.set_center_freq(self.freq)
self.usink1.set_center_freq(self.freq)
self.usink0.clear_command_time()
self.usink1.clear_command_time()
################
After the changes, the performance improved, but still not what I want. I
am wondering whether it is possible to implement a MIMO system for certain
applications without PPS signal especially when the application doesn't
require that much time precision. If yes, is there anything else I can do
to improve the current system or is there anything wrong with my current
configuration?
Thanks,
Yang
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------------------------------
Message: 10
Date: Tue, 19 Apr 2016 20:45:56 -0400
From: "Marcus D. Leech" <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] building a MIMO system without PPS signal
Message-ID: <[email protected]>
Content-Type: text/plain; charset="windows-1252"; Format="flowed"
On 04/19/2016 07:43 PM, Yang Liu via USRP-users wrote:
> Dear all,
>
> Now I am trying to build a 2x2 MIMO system using 4 USRP N210s, and
> external 10MHz clock is used for frequency synchronization. However,
> PPS signal is not available.
>
> the setup is: each USRP is connected to the PC directly via ethernet
> cable and thus, all 4 USRPs (2 as transmitters, 2 as receivers) are
> controlled by the same host computer. 2 transmitting USRPs are
> synchronized by one 10MHz clock, and 2 receiving USRPs are
> synchronized by another 10MHz clock.
>
> In the beginning, I thought that our application doesn't require time
> precision on every node, so frequency synchronization suffices.
> However, the experiment acted poorly. The bit error rate at the
> receiver side was very large. I thought it should be the problem with
> time synchronization (Since the code I had works properly when the
> USRPs are synchronizied by MIMO cables), so I followed some
> suggestions online to achieve time synchronization at TX/RX:
>
> https://www.ruby-forum.com/topic/4409521
> http://files.ettus.com/manual/page_sync.html
>
> here is the code for USRP N210 configuration at the transmitter side
> (configuration at RX is very similar):
> #################
> transmitter
> #################
> self.usink0=uhd.usrp_sink(device_addr="addr0=192.168.10.2",
> io_type=uhd.io_type.COMPLEX_FLOAT32, num_channels=1)
> self.usink1=uhd.usrp_sink(device_addr="addr0=192.168.10.4",
> io_type=uhd.io_type.COMPLEX_FLOAT32, num_channels=1)
> self.usink0.set_clock_source("external")
> self.usink1.set_clock_source("external")
> self.usink0.set_time_now(uhd.time_spec_t(time.time())) #set the time
> registers immediately
> self.usink1.set_time_now(uhd.time_spec_t(time.time()))
> self.usink0.set_samp_rate(self.samp_rate)
> self.usink1.set_samp_rate(self.samp_rate)
> self.usink0.set_gain(self.gain)
> self.usink1.set_gain(self.gain)
> self.usink0.set_antenna(self.antenna)
> self.usink1.set_antenna(self.antenna)
> future=time.time()+0.5
> self.usink0.set_command_time(uhd.time_spec_t(future))
> self.usink1.set_command_time(uhd.time_spec_t(future))
> self.usink0.set_center_freq(self.freq)
> self.usink1.set_center_freq(self.freq)
> self.usink0.clear_command_time()
> self.usink1.clear_command_time()
> ################
>
>
> After the changes, the performance improved, but still not what I
> want. I am wondering whether it is possible to implement a MIMO system
> for certain applications without PPS signal especially when the
> application doesn't require that much time precision. If yes, is there
> anything else I can do to improve the current system or is there
> anything wrong with my current configuration?
>
> Thanks,
> Yang
>
>
You want a single multi-usrp object, not two separate ones. That will help.
Also, you do a set_time_now() with two separate calls to time.time(),
which will return two different times. It's likely better to use a
single time,
rather than two different ones. Since you're not using a
set_time_next_pps() or set_time_unknown_pps(), you'll have to evaluate the
difference between the two yourself, in your system.
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------------------------------
Message: 11
Date: Tue, 19 Apr 2016 22:21:45 -0400
From: "Marcus D. Leech" <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] Loopback of RFNoC version
Message-ID: <[email protected]>
Content-Type: text/plain; charset=windows-1252; format=flowed
On 04/19/2016 12:30 PM, Zhihong Luo via USRP-users wrote:
> Hi all,
>
> Is it right that for RFNoC version,one Radio block can only serve as
> either RX or TX, so that we can not do loop back on one motherboard? I
> used to be able to do it on the ordinary version.
>
> Thanks,
> Zhihong
>
Loopback functionality is being worked on, I believe as part of the
radio-redo. Martin and/or Jonathan would have a better idea what the
horizon is for this.
------------------------------
Message: 12
Date: Tue, 19 Apr 2016 19:44:26 -0700
From: "jj08" <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] External reference for USRP2
Message-ID: <1063158321000000009736706@www>
Content-Type: text/plain; charset="utf-8"
Hi M,
Yes, that was it- I plotted large number of samples, and there was it!
Thank you for the insight.
Cheers,
jj
--From: [email protected]
--To: [email protected]
--Date: 4/19/2016 12:15:09 PM
--Subject: Re: [USRP-users] External reference for USRP2
Have you tried setting a larger offset (e.g. 1 MHz or even larger)? At
10 Msps you need 1e4 samples to see one single wave cycle, and it seems
you're plotting a few hundred.
Also, there's tools like GNU Radio that make this kind of thing much,
much easier to test.
Cheers,
M
On 04/19/2016 10:06 AM, jj08 via USRP-users wrote:
> Hello Experts,
>
> I am brand new to USRP.
>
> I have connected analog signal generator's sine wave output (999.999
> MHz, -30dBm) to the USRP2 (Rx2).
>
> A Rb 10 MHz freq. standard provides reference signal to the signal
> generator as well as to the USRP2.
>
> I have set the carrier frequency of the radio at 1GHz.
>
> I am trying to see the output of rx_stream.
>
> I expected a 1kHz sine wave signal, but I just get a flat line. I want
> to see a sine curve, but have no idea what other parameters do I need
> to provide and where and how.
>
> Here are the values I have set:
>
> //-----------------------------------------------------
>
> //setup the program options
> po::options_description desc("Allowed options");
> ("args", po::value(&args)->default_value(""),
> "multi uhd device address args") ("type",
> po::value(&type)->default_value("short"), "sample type:
> double, float,
> or short") ("nsamps",
> po::value(&total_num_samps)->default_value(0),
> "total number of samples to receive") ("duration",
> po::value(&total_time)->default_value(0), "total number of seconds to
> receive") ("spb", po::value(&spb)->default_value(10000),
> "samples per
> buffer") ("rate", po::value(&rate)->default_value(10e6),
> "rate of
> incoming samples") ("freq",
> po::value(&freq)->default_value(1e9), "RF
> center frequency in Hz") ("gain", po::value(&gain),
> "gain for the RF
> chain") ("ant",
> po::value(&ant)->default_value("RX2"), "antenna
> selection") ("subdev", po::value(&subdev), "subdevice
> specification")
> ("bw", po::value(&bw), "analog frontend filter bandwidth in
> Hz") ("ref",
> po::value(&ref)->default_value("external"), "reference source
> (internal,
> external, mimo)") ("wirefmt",
> po::value(&wirefmt)->default_value("sc16"), "wire format (sc8
> or sc16)
> ("setup", po::value(&setup_time)->default_value(1.0),
> "seconds of setup
> time") ("progress", "periodically display short-term
> bandwidth")
> ("stats", "show average bandwidth on exit")
> ("sizemap", "track packet
> size and display breakdown on exit") ("null", "run
> without writing to
> file") ("continue", "don't abort on a bad packet")
> ("skip-lo", "skip
> checking LO lock status") ("int-n", "tune USRP with
> integer-N tuning") ;
> //----------------------------------------------
>
> When I set reference source to "internal", and with all other
> setting as
> it is, I *do* get a desired output, a nice looking sine wave.
>
> What should I be doing to get a sine wave while using an external ref.?
>
> Any pointers would be highly appreciated.
>
> Thank you very much for your time and guidance.
>
> Cheers!
>
>
> -------------------------
> Online Storage & Sharing, Online Backup, FTP / Email Server Hosting and
> More.
> Drive Headquarters. Top quality services designed for business!
> Sign up free at: www.DriveHQ.com >
-------------------------
Online Storage & Sharing, Online Backup, FTP / Email Server Hosting and More.
Drive Headquarters. Top quality services designed for business! Sign up free
at: www.DriveHQ.com
.
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------------------------------
Message: 13
Date: Tue, 19 Apr 2016 23:32:46 -0400
From: "Marcus D. Leech" <[email protected]>
To: Yang Liu <[email protected]>, "[email protected]"
<[email protected]>
Subject: Re: [USRP-users] building a MIMO system without PPS signal
Message-ID: <[email protected]>
Content-Type: text/plain; charset="utf-8"; Format="flowed"
On 04/19/2016 11:10 PM, Yang Liu wrote:
> Hi Marcus,
>
> Got it!
>
> Another question: how can I have access to multi_usrp in python? I
> didn't find it in gnuradio.
>
> Thanks,
> Yang
>
gr-uhd exposes multi-usrp.
Best thing to do is to create a very simple GRC-based flow-graph with
both devices in the same USRP source (and sink), and look at the
generated code.
> On Tue, Apr 19, 2016 at 9:29 PM, Marcus D. Leech <[email protected]
> <mailto:[email protected]>> wrote:
>
> On 04/19/2016 09:00 PM, Yang Liu wrote:
>> Hi Marcus,
>>
>> Thanks a lot for your help. I will try multi-usrp object!
>>
>> Since the PPS signal is not available so I don't use
>> set_time_next_pps() or set_time_unknown_pps(). How should I
>> evaluate the difference? I don't get this part.
>>
>> Thanks,
>> Yang
> You have two separate calls to set_time_now(), each calling
> time.time() separately. That time.time() call is going to return
> separate times.
> You should evaluation the difference between:
>
> usrp1.set_time_now(time.time())
> usrp2.set_time_now(time.time())
>
> and:
>
> t = time.time()
>
> usrp1.set_time_now(t)
> usrp1.set_time_now(t)
>
>
>
>>
>> On Tue, Apr 19, 2016 at 8:45 PM, Marcus D. Leech via USRP-users
>> <[email protected] <mailto:[email protected]>>
>> wrote:
>>
>> On 04/19/2016 07:43 PM, Yang Liu via USRP-users wrote:
>>> Dear all,
>>>
>>> Now I am trying to build a 2x2 MIMO system using 4 USRP
>>> N210s, and external 10MHz clock is used for frequency
>>> synchronization. However, PPS signal is not available.
>>>
>>> the setup is: each USRP is connected to the PC directly via
>>> ethernet cable and thus, all 4 USRPs (2 as transmitters, 2
>>> as receivers) are controlled by the same host computer. 2
>>> transmitting USRPs are synchronized by one 10MHz clock, and
>>> 2 receiving USRPs are synchronized by another 10MHz clock.
>>>
>>> In the beginning, I thought that our application doesn't
>>> require time precision on every node, so frequency
>>> synchronization suffices. However, the experiment acted
>>> poorly. The bit error rate at the receiver side was very
>>> large. I thought it should be the problem with time
>>> synchronization (Since the code I had works properly when
>>> the USRPs are synchronizied by MIMO cables), so I followed
>>> some suggestions online to achieve time synchronization at
>>> TX/RX:
>>>
>>> https://www.ruby-forum.com/topic/4409521
>>> http://files.ettus.com/manual/page_sync.html
>>>
>>> here is the code for USRP N210 configuration at the
>>> transmitter side (configuration at RX is very similar):
>>> #################
>>> transmitter
>>> #################
>>> self.usink0=uhd.usrp_sink(device_addr="addr0=192.168.10.2",
>>> io_type=uhd.io_type.COMPLEX_FLOAT32, num_channels=1)
>>> self.usink1=uhd.usrp_sink(device_addr="addr0=192.168.10.4",
>>> io_type=uhd.io_type.COMPLEX_FLOAT32, num_channels=1)
>>> self.usink0.set_clock_source("external")
>>> self.usink1.set_clock_source("external")
>>> self.usink0.set_time_now(uhd.time_spec_t(time.time()))
>>> #set the time registers immediately
>>> self.usink1.set_time_now(uhd.time_spec_t(time.time()))
>>> self.usink0.set_samp_rate(self.samp_rate)
>>> self.usink1.set_samp_rate(self.samp_rate)
>>> self.usink0.set_gain(self.gain)
>>> self.usink1.set_gain(self.gain)
>>> self.usink0.set_antenna(self.antenna)
>>> self.usink1.set_antenna(self.antenna)
>>> future=time.time()+0.5
>>> self.usink0.set_command_time(uhd.time_spec_t(future))
>>> self.usink1.set_command_time(uhd.time_spec_t(future))
>>> self.usink0.set_center_freq(self.freq)
>>> self.usink1.set_center_freq(self.freq)
>>> self.usink0.clear_command_time()
>>> self.usink1.clear_command_time()
>>> ################
>>>
>>>
>>> After the changes, the performance improved, but still not
>>> what I want. I am wondering whether it is possible to
>>> implement a MIMO system for certain applications without PPS
>>> signal especially when the application doesn't require that
>>> much time precision. If yes, is there anything else I can do
>>> to improve the current system or is there anything wrong
>>> with my current configuration?
>>>
>>> Thanks,
>>> Yang
>>>
>>>
>> You want a single multi-usrp object, not two separate ones.
>> That will help.
>>
>> Also, you do a set_time_now() with two separate calls to
>> time.time(), which will return two different times. It's
>> likely better to use a single time,
>> rather than two different ones. Since you're not using a
>> set_time_next_pps() or set_time_unknown_pps(), you'll have to
>> evaluate the
>> difference between the two yourself, in your system.
>>
>>
>>
>>
>> _______________________________________________
>> USRP-users mailing list
>> [email protected] <mailto:[email protected]>
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>>
>
>
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Message: 14
Date: Tue, 19 Apr 2016 23:39:35 -0700
From: Ian Buckley <[email protected]>
To: "Marcus D. Leech" <[email protected]>
Cc: Yang Liu <[email protected]>, "[email protected]"
<[email protected]>
Subject: Re: [USRP-users] building a MIMO system without PPS signal
Message-ID:
<cam_0ocfrone6omtkwtaxjs_xyndhetdvodsgye3hzhgkqwu...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Its useful to bear in mind that a PPS signal is nothing other than a
synchronization pulse in this type of system setup...it doesn't need to run
continuously, nor do you need an extremely accurate absolute time value.
All you really need is the 4 time counters in the USRP's you are using to
count in synchronization. So it's entirely possible to be creative and use
the 10MHz clock + small circuit of your own creation to generate a single
logic transition on the PPS inputs allowing you to use a command like
set_time_next_pps() to get align all the USRP's in time (relative to each
other).
-Ian
On Tue, Apr 19, 2016 at 8:32 PM, Marcus D. Leech via USRP-users <
[email protected]> wrote:
> On 04/19/2016 11:10 PM, Yang Liu wrote:
>
> Hi Marcus,
>
> Got it!
>
> Another question: how can I have access to multi_usrp in python? I didn't
> find it in gnuradio.
>
> Thanks,
> Yang
>
> gr-uhd exposes multi-usrp.
>
> Best thing to do is to create a very simple GRC-based flow-graph with both
> devices in the same USRP source (and sink), and look at the
> generated code.
>
>
> On Tue, Apr 19, 2016 at 9:29 PM, Marcus D. Leech <[email protected]>
> wrote:
>
>> On 04/19/2016 09:00 PM, Yang Liu wrote:
>>
>> Hi Marcus,
>>
>> Thanks a lot for your help. I will try multi-usrp object!
>>
>> Since the PPS signal is not available so I don't use set_time_next_pps()
>> or set_time_unknown_pps(). How should I evaluate the difference? I don't
>> get this part.
>>
>> Thanks,
>> Yang
>>
>> You have two separate calls to set_time_now(), each calling time.time()
>> separately. That time.time() call is going to return separate times.
>> You should evaluation the difference between:
>>
>> usrp1.set_time_now(time.time())
>> usrp2.set_time_now(time.time())
>>
>> and:
>>
>> t = time.time()
>>
>> usrp1.set_time_now(t)
>> usrp1.set_time_now(t)
>>
>>
>>
>>
>> On Tue, Apr 19, 2016 at 8:45 PM, Marcus D. Leech via USRP-users <
>> [email protected]> wrote:
>>
>>> On 04/19/2016 07:43 PM, Yang Liu via USRP-users wrote:
>>>
>>> Dear all,
>>>
>>> Now I am trying to build a 2x2 MIMO system using 4 USRP N210s, and
>>> external 10MHz clock is used for frequency synchronization. However, PPS
>>> signal is not available.
>>>
>>> the setup is: each USRP is connected to the PC directly via ethernet
>>> cable and thus, all 4 USRPs (2 as transmitters, 2 as receivers) are
>>> controlled by the same host computer. 2 transmitting USRPs are synchronized
>>> by one 10MHz clock, and 2 receiving USRPs are synchronized by another 10MHz
>>> clock.
>>>
>>> In the beginning, I thought that our application doesn't require time
>>> precision on every node, so frequency synchronization suffices. However,
>>> the experiment acted poorly. The bit error rate at the receiver side was
>>> very large. I thought it should be the problem with time synchronization
>>> (Since the code I had works properly when the USRPs are synchronizied by
>>> MIMO cables), so I followed some suggestions online to achieve time
>>> synchronization at TX/RX:
>>>
>>> https://www.ruby-forum.com/topic/4409521
>>> http://files.ettus.com/manual/page_sync.html
>>>
>>> here is the code for USRP N210 configuration at the transmitter side
>>> (configuration at RX is very similar):
>>> #################
>>> transmitter
>>> #################
>>> self.usink0=uhd.usrp_sink(device_addr="addr0=192.168.10.2",
>>> io_type=uhd.io_type.COMPLEX_FLOAT32, num_channels=1)
>>> self.usink1=uhd.usrp_sink(device_addr="addr0=192.168.10.4",
>>> io_type=uhd.io_type.COMPLEX_FLOAT32, num_channels=1)
>>> self.usink0.set_clock_source("external")
>>> self.usink1.set_clock_source("external")
>>> self.usink0.set_time_now(uhd.time_spec_t(time.time())) #set the time
>>> registers immediately
>>> self.usink1.set_time_now(uhd.time_spec_t(time.time()))
>>> self.usink0.set_samp_rate(self.samp_rate)
>>> self.usink1.set_samp_rate(self.samp_rate)
>>> self.usink0.set_gain(self.gain)
>>> self.usink1.set_gain(self.gain)
>>> self.usink0.set_antenna(self.antenna)
>>> self.usink1.set_antenna(self.antenna)
>>> future=time.time()+0.5
>>> self.usink0.set_command_time(uhd.time_spec_t(future))
>>> self.usink1.set_command_time(uhd.time_spec_t(future))
>>> self.usink0.set_center_freq(self.freq)
>>> self.usink1.set_center_freq(self.freq)
>>> self.usink0.clear_command_time()
>>> self.usink1.clear_command_time()
>>> ################
>>>
>>>
>>> After the changes, the performance improved, but still not what I want.
>>> I am wondering whether it is possible to implement a MIMO system for
>>> certain applications without PPS signal especially when the application
>>> doesn't require that much time precision. If yes, is there anything else I
>>> can do to improve the current system or is there anything wrong with my
>>> current configuration?
>>>
>>> Thanks,
>>> Yang
>>>
>>>
>>> You want a single multi-usrp object, not two separate ones. That will
>>> help.
>>>
>>> Also, you do a set_time_now() with two separate calls to time.time(),
>>> which will return two different times. It's likely better to use a single
>>> time,
>>> rather than two different ones. Since you're not using a
>>> set_time_next_pps() or set_time_unknown_pps(), you'll have to evaluate the
>>> difference between the two yourself, in your system.
>>>
>>>
>>>
>>>
>>> _______________________________________________
>>> USRP-users mailing list
>>> [email protected]
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>>
>>
>>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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------------------------------
Message: 15
Date: Wed, 20 Apr 2016 11:39:46 +0200
From: BHUSHAN PAWAR <[email protected]>
To: Jonathon Pendlum <[email protected]>
Cc: Nikos Balkanas <[email protected]>,
"[email protected]" <[email protected]>,
[email protected]
Subject: Re: [USRP-users] E310 : Interfacing ZynQ 7020 with AD 9361
RFIC and Filter Banks
Message-ID:
<cafvcn__c2hezsi3qzjrrgwvodozr0njk0dgnx9ndwz_t8xv...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Dear Jonathon,
Thanks for your reply. I followed your suggestion and and to build the
project using command 'make E310 GUI=1'.
It opened the GUI for Vivado, however before I could save the project there
was an error and Vivado was closed automatically. Below are the lines from
terminal also I am attaching the log file with this email,
[pawa_bh@ohff24 e300]$ chmod u+x setupenv.sh
[pawa_bh@ohff24 e300]$ . setupenv.sh
Setting up X3x0 FPGA build environment (64-bit)...
bash:
/opt/Xilinx/Vivado_HLS/Vivado/2014.4/.settings64-Vivado_High_Level_Synthesis.sh:
Datei oder Verzeichnis nicht gefunden
- Vivado: Found (/opt/Xilinx/Vivado/Vivado/2014.4/bin)
Environment successfully initialized.
[pawa_bh@ohff24 e300]$ make E310 GUI=1
make -f Makefile.e300.inc bin NAME=E310 ARCH=zynq PART_ID=xc7z020/clg484/-1
EXTRA_DEFS="E310"
make[1]: Entering directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300'
Vivado v2014.4 (64-bit)
****** Vivado v2014.4 (64-bit)
**** SW Build 1071353 on Tue Nov 18 16:48:31 MST 2014
**** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014
** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
start_gui
Abnormal program termination (11)
Please check
'/home/pawa_bh/uhd/fpga-src/usrp3/top/e300/build-E310/hs_err_pid12758.log'
for details
make[1]: *** [bin] Fehler 139
make[1]: Leaving directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300'
make: *** [E310] Fehler 2
[pawa_bh@ohff24 e300]$
I tried building the project with only make E310 command and the bit file
was generated without any error.
Kindly help me to resolve this issue.
*Thanks & Regards,*
*Bhushan R.V. Pawar.*
On Mon, Feb 15, 2016 at 11:14 PM, Jonathon Pendlum <
[email protected]> wrote:
> Hi Pawar,
>
> It looks like you created a Vivado project file and then manually imported
> source files. I would suggest instead running make with GUI=1, i.e. make
> GUI=1 E310. This will load the Vivado GUI and you can save a project file
> from there (File->Save Project As...).
>
>
>
> Jonathon
>
> On Mon, Feb 15, 2016 at 8:05 AM, Nikos Balkanas via USRP-users <
> [email protected]> wrote:
>
>> Hi,
>>
>> Did you followed the Makefile procedure indicated by James? What target
>> did you build?
>>
>> Nikos
>>
>> On Mon, Feb 15, 2016 at 5:26 PM, BHUSHAN PAWAR <
>> [email protected]> wrote:
>>
>>> Errors:
>>>
>>> [Synthv8-448] named port connection 'GPIO_I' does not exist for instance
>>> 'inst_processing_system7' of module 'processing_system7_1' [e3xx_ps.v.263]
>>> (85 more like this)
>>>
>>> [Synthv8-285] failed synthesizing module 'axi4_fifo_512x64'
>>> [axi4_fifo_512x64_stub.v.7]
>>> (2 more like this)
>>>
>>> *Thanks & Regards,*
>>>
>>> *Bhushan R.V. Pawar.*
>>> *(+49-17685263152 <%28%2B49-17685263152>)*
>>>
>>>
>>> On Mon, Feb 15, 2016 at 4:08 PM, BHUSHAN PAWAR <
>>> [email protected]> wrote:
>>>
>>>> Hi all,
>>>>
>>>> I am using the source code from Github usrp3/top/e300 and trying to
>>>> synthesize the code. However, I am getting these errors. Kindly help.
>>>>
>>>> [image: Inline image 2][image: Inline image 1]
>>>>
>>>>
>>>> *Thanks !!*
>>>>
>>>>
>>>> On Mon, Feb 15, 2016 at 1:22 PM, Nikos Balkanas <[email protected]>
>>>> wrote:
>>>>
>>>>> Hi Pawar,
>>>>>
>>>>> The FPGA sources are to modify the FPGA. The FPGA is larger than the
>>>>> image it currently holds. Many people use it to add aditional filters,
>>>>> FFTs, etc.
>>>>> Adding on top of what already exists and is needed for correct
>>>>> functionality...But you need to know Vivado for that. Check also RFNOC, it
>>>>> may be easier:)
>>>>>
>>>>> PS: Plz keep discussion in group, so that others may benefit as well...
>>>>>
>>>>> HTH,
>>>>> Nikos
>>>>>
>>>>> On Mon, Feb 15, 2016 at 2:11 PM, BHUSHAN PAWAR <
>>>>> [email protected]> wrote:
>>>>>
>>>>>> Hi Nikos,
>>>>>>
>>>>>> Thanks for the reply.
>>>>>>
>>>>>> Then can you explain me what is the real use of the FPGA code on
>>>>>> usrp3/top/e300 subdirectory on github.
>>>>>>
>>>>>> How can I use this code to get started?
>>>>>>
>>>>>>
>>>>>>
>>>>>> *Thanks & Regards,*
>>>>>>
>>>>>> *Bhushan R.V. Pawar.*
>>>>>>
>>>>>>
>>>>>> On Mon, Feb 15, 2016 at 12:06 PM, Nikos Balkanas <[email protected]
>>>>>> > wrote:
>>>>>>
>>>>>>> Hi,
>>>>>>>
>>>>>>> Have you also tried vivado forums? They can help more than what we
>>>>>>> can here...
>>>>>>> Plz post your errors. Recently started on vivado myself, and the
>>>>>>> only errors I got were from licensing issues for my FPGA.
>>>>>>> I have an X300
>>>>>>>
>>>>>>> HTH,
>>>>>>> Nikos
>>>>>>>
>>>>>>> On Mon, Feb 15, 2016 at 12:54 PM, BHUSHAN PAWAR via USRP-users <
>>>>>>> [email protected]> wrote:
>>>>>>>
>>>>>>>> Dear Moritz,
>>>>>>>>
>>>>>>>> Thank you for the reply.
>>>>>>>>
>>>>>>>> I want to use E310 as multi channel transmitter and receiver and
>>>>>>>> want to test it using signal generator and oscilloscope.
>>>>>>>>
>>>>>>>> I tried to import the code from usrp3/top/e300 subdirectory into
>>>>>>>> Vivado 2015.4 but it is giving many errors when I try to synthesize it.
>>>>>>>>
>>>>>>>> Can you explain me step by step, how to work with E310.
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> *Thanks !!*
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer <
>>>>>>>> [email protected]> wrote:
>>>>>>>>
>>>>>>>>> Hi Bhushan,
>>>>>>>>>
>>>>>>>>> On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users
>>>>>>>>> <[email protected]> wrote:
>>>>>>>>> > Hello,
>>>>>>>>> >
>>>>>>>>> > I am trying to build multi channel transmitter and receiver
>>>>>>>>> using USRP E310.
>>>>>>>>>
>>>>>>>>> all our code for E310 is open-source. Feel free to peruse our
>>>>>>>>> github.
>>>>>>>>> On the FPGA side you might wanna look at the usrp3/top/e300
>>>>>>>>> subdirectory [1].
>>>>>>>>>
>>>>>>>>> If you let us know what exactly you're trying to do, people can
>>>>>>>>> help
>>>>>>>>> you out easier.
>>>>>>>>> > However I am new to FPGA programming, hence I am facing a lot of
>>>>>>>>> challenges
>>>>>>>>> > in interfacing ZynQ board with the transceiver and filter banks
>>>>>>>>> in Vivado
>>>>>>>>> > 2015.4.
>>>>>>>>> > Is to possible to get few demo projects which might help me to
>>>>>>>>> understand
>>>>>>>>> > the data flow in the simple transmitter and receiver
>>>>>>>>> application? Kindly
>>>>>>>>> > share few useful documents which will help me to understand the
>>>>>>>>> above
>>>>>>>>> > problem.
>>>>>>>>>
>>>>>>>>> Again, all our code for E310 is open source (apart from Xilinx IP).
>>>>>>>>> Feel free to dig through the code.
>>>>>>>>> The filter bank settings are documented in the UHD manual [2].
>>>>>>>>>
>>>>>>>>> Good luck,
>>>>>>>>>
>>>>>>>>> Moritz
>>>>>>>>>
>>>>>>>>> [1]
>>>>>>>>> https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300
>>>>>>>>> [2] http://files.ettus.com/manual/page_usrp_e3x0.html
>>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> _______________________________________________
>>>>>>>> USRP-users mailing list
>>>>>>>> [email protected]
>>>>>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>
>>>>>
>>>>
>>>
>>
>> _______________________________________________
>> USRP-users mailing list
>> [email protected]
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>>
>
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------------------------------
Message: 16
Date: Wed, 20 Apr 2016 11:45:33 +0200
From: BHUSHAN PAWAR <[email protected]>
To: Jonathon Pendlum <[email protected]>
Cc: Nikos Balkanas <[email protected]>,
"[email protected]" <[email protected]>,
[email protected]
Subject: Re: [USRP-users] E310 : Interfacing ZynQ 7020 with AD 9361
RFIC and Filter Banks
Message-ID:
<cafvcn_9ewjs17myassiybwqer7shaobdnk35xjm+tb2hemb...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Dear Jonathon,
Thanks for your reply. I followed your suggestion and and to build the
project using command 'make E310 GUI=1'.
It opened the GUI for Vivado, however before I could save the project there
was an error and Vivado was closed automatically. Below are the lines from
terminal also I am attaching the log file with this email,
[pawa_bh@ohff24 e300]$ chmod u+x setupenv.sh
[pawa_bh@ohff24 e300]$ . setupenv.sh
Setting up X3x0 FPGA build environment (64-bit)...
bash:
/opt/Xilinx/Vivado_HLS/Vivado/2014.4/.settings64-Vivado_High_Level_Synthesis.sh:
Datei oder Verzeichnis nicht gefunden
- Vivado: Found (/opt/Xilinx/Vivado/Vivado/2014.4/bin)
Environment successfully initialized.
[pawa_bh@ohff24 e300]$ make E310 GUI=1
make -f Makefile.e300.inc bin NAME=E310 ARCH=zynq PART_ID=xc7z020/clg484/-1
EXTRA_DEFS="E310"
make[1]: Entering directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300'
Vivado v2014.4 (64-bit)
****** Vivado v2014.4 (64-bit)
**** SW Build 1071353 on Tue Nov 18 16:48:31 MST 2014
**** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014
** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
start_gui
Abnormal program termination (11)
Please check
'/home/pawa_bh/uhd/fpga-src/usrp3/top/e300/build-E310/hs_err_pid12758.log'
for details
make[1]: *** [bin] Fehler 139
make[1]: Leaving directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300'
make: *** [E310] Fehler 2
[pawa_bh@ohff24 e300]$
I tried building the project with only make E310 command and the bit file
was generated without any error.
Kindly help me to resolve this issue.
*Thanks & Regards,*
*Bhushan R.V. Pawar.*
*(+49-17685263152)*
On Wed, Apr 20, 2016 at 11:39 AM, BHUSHAN PAWAR <[email protected]>
wrote:
> Dear Jonathon,
>
> Thanks for your reply. I followed your suggestion and and to build the
> project using command 'make E310 GUI=1'.
> It opened the GUI for Vivado, however before I could save the project
> there was an error and Vivado was closed automatically. Below are the lines
> from terminal also I am attaching the log file with this email,
>
> [pawa_bh@ohff24 e300]$ chmod u+x setupenv.sh
> [pawa_bh@ohff24 e300]$ . setupenv.sh
> Setting up X3x0 FPGA build environment (64-bit)...
> bash:
> /opt/Xilinx/Vivado_HLS/Vivado/2014.4/.settings64-Vivado_High_Level_Synthesis.sh:
> Datei oder Verzeichnis nicht gefunden
> - Vivado: Found (/opt/Xilinx/Vivado/Vivado/2014.4/bin)
>
> Environment successfully initialized.
> [pawa_bh@ohff24 e300]$ make E310 GUI=1
> make -f Makefile.e300.inc bin NAME=E310 ARCH=zynq
> PART_ID=xc7z020/clg484/-1 EXTRA_DEFS="E310"
> make[1]: Entering directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300'
> Vivado v2014.4 (64-bit)
>
> ****** Vivado v2014.4 (64-bit)
> **** SW Build 1071353 on Tue Nov 18 16:48:31 MST 2014
> **** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014
> ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
>
> start_gui
> Abnormal program termination (11)
> Please check
> '/home/pawa_bh/uhd/fpga-src/usrp3/top/e300/build-E310/hs_err_pid12758.log'
> for details
> make[1]: *** [bin] Fehler 139
> make[1]: Leaving directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300'
> make: *** [E310] Fehler 2
> [pawa_bh@ohff24 e300]$
>
>
> I tried building the project with only make E310 command and the bit file
> was generated without any error.
> Kindly help me to resolve this issue.
>
>
> *Thanks & Regards,*
>
> *Bhushan R.V. Pawar.*
>
>
> On Mon, Feb 15, 2016 at 11:14 PM, Jonathon Pendlum <
> [email protected]> wrote:
>
>> Hi Pawar,
>>
>> It looks like you created a Vivado project file and then manually
>> imported source files. I would suggest instead running make with GUI=1,
>> i.e. make GUI=1 E310. This will load the Vivado GUI and you can save a
>> project file from there (File->Save Project As...).
>>
>>
>>
>> Jonathon
>>
>> On Mon, Feb 15, 2016 at 8:05 AM, Nikos Balkanas via USRP-users <
>> [email protected]> wrote:
>>
>>> Hi,
>>>
>>> Did you followed the Makefile procedure indicated by James? What target
>>> did you build?
>>>
>>> Nikos
>>>
>>> On Mon, Feb 15, 2016 at 5:26 PM, BHUSHAN PAWAR <
>>> [email protected]> wrote:
>>>
>>>> Errors:
>>>>
>>>> [Synthv8-448] named port connection 'GPIO_I' does not exist for
>>>> instance 'inst_processing_system7' of module 'processing_system7_1'
>>>> [e3xx_ps.v.263]
>>>> (85 more like this)
>>>>
>>>> [Synthv8-285] failed synthesizing module 'axi4_fifo_512x64'
>>>> [axi4_fifo_512x64_stub.v.7]
>>>> (2 more like this)
>>>>
>>>> *Thanks & Regards,*
>>>>
>>>> *Bhushan R.V. Pawar.*
>>>> *(+49-17685263152 <%28%2B49-17685263152>)*
>>>>
>>>>
>>>> On Mon, Feb 15, 2016 at 4:08 PM, BHUSHAN PAWAR <
>>>> [email protected]> wrote:
>>>>
>>>>> Hi all,
>>>>>
>>>>> I am using the source code from Github usrp3/top/e300 and trying to
>>>>> synthesize the code. However, I am getting these errors. Kindly help.
>>>>>
>>>>> [image: Inline image 2][image: Inline image 1]
>>>>>
>>>>>
>>>>> *Thanks !!*
>>>>>
>>>>>
>>>>> On Mon, Feb 15, 2016 at 1:22 PM, Nikos Balkanas <[email protected]>
>>>>> wrote:
>>>>>
>>>>>> Hi Pawar,
>>>>>>
>>>>>> The FPGA sources are to modify the FPGA. The FPGA is larger than the
>>>>>> image it currently holds. Many people use it to add aditional filters,
>>>>>> FFTs, etc.
>>>>>> Adding on top of what already exists and is needed for correct
>>>>>> functionality...But you need to know Vivado for that. Check also RFNOC,
>>>>>> it
>>>>>> may be easier:)
>>>>>>
>>>>>> PS: Plz keep discussion in group, so that others may benefit as
>>>>>> well...
>>>>>>
>>>>>> HTH,
>>>>>> Nikos
>>>>>>
>>>>>> On Mon, Feb 15, 2016 at 2:11 PM, BHUSHAN PAWAR <
>>>>>> [email protected]> wrote:
>>>>>>
>>>>>>> Hi Nikos,
>>>>>>>
>>>>>>> Thanks for the reply.
>>>>>>>
>>>>>>> Then can you explain me what is the real use of the FPGA code on
>>>>>>> usrp3/top/e300 subdirectory on github.
>>>>>>>
>>>>>>> How can I use this code to get started?
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> *Thanks & Regards,*
>>>>>>>
>>>>>>> *Bhushan R.V. Pawar.*
>>>>>>>
>>>>>>>
>>>>>>> On Mon, Feb 15, 2016 at 12:06 PM, Nikos Balkanas <
>>>>>>> [email protected]> wrote:
>>>>>>>
>>>>>>>> Hi,
>>>>>>>>
>>>>>>>> Have you also tried vivado forums? They can help more than what we
>>>>>>>> can here...
>>>>>>>> Plz post your errors. Recently started on vivado myself, and the
>>>>>>>> only errors I got were from licensing issues for my FPGA.
>>>>>>>> I have an X300
>>>>>>>>
>>>>>>>> HTH,
>>>>>>>> Nikos
>>>>>>>>
>>>>>>>> On Mon, Feb 15, 2016 at 12:54 PM, BHUSHAN PAWAR via USRP-users <
>>>>>>>> [email protected]> wrote:
>>>>>>>>
>>>>>>>>> Dear Moritz,
>>>>>>>>>
>>>>>>>>> Thank you for the reply.
>>>>>>>>>
>>>>>>>>> I want to use E310 as multi channel transmitter and receiver and
>>>>>>>>> want to test it using signal generator and oscilloscope.
>>>>>>>>>
>>>>>>>>> I tried to import the code from usrp3/top/e300 subdirectory into
>>>>>>>>> Vivado 2015.4 but it is giving many errors when I try to synthesize
>>>>>>>>> it.
>>>>>>>>>
>>>>>>>>> Can you explain me step by step, how to work with E310.
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> *Thanks !!*
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer <
>>>>>>>>> [email protected]> wrote:
>>>>>>>>>
>>>>>>>>>> Hi Bhushan,
>>>>>>>>>>
>>>>>>>>>> On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users
>>>>>>>>>> <[email protected]> wrote:
>>>>>>>>>> > Hello,
>>>>>>>>>> >
>>>>>>>>>> > I am trying to build multi channel transmitter and receiver
>>>>>>>>>> using USRP E310.
>>>>>>>>>>
>>>>>>>>>> all our code for E310 is open-source. Feel free to peruse our
>>>>>>>>>> github.
>>>>>>>>>> On the FPGA side you might wanna look at the usrp3/top/e300
>>>>>>>>>> subdirectory [1].
>>>>>>>>>>
>>>>>>>>>> If you let us know what exactly you're trying to do, people can
>>>>>>>>>> help
>>>>>>>>>> you out easier.
>>>>>>>>>> > However I am new to FPGA programming, hence I am facing a lot
>>>>>>>>>> of challenges
>>>>>>>>>> > in interfacing ZynQ board with the transceiver and filter banks
>>>>>>>>>> in Vivado
>>>>>>>>>> > 2015.4.
>>>>>>>>>> > Is to possible to get few demo projects which might help me to
>>>>>>>>>> understand
>>>>>>>>>> > the data flow in the simple transmitter and receiver
>>>>>>>>>> application? Kindly
>>>>>>>>>> > share few useful documents which will help me to understand the
>>>>>>>>>> above
>>>>>>>>>> > problem.
>>>>>>>>>>
>>>>>>>>>> Again, all our code for E310 is open source (apart from Xilinx
>>>>>>>>>> IP).
>>>>>>>>>> Feel free to dig through the code.
>>>>>>>>>> The filter bank settings are documented in the UHD manual [2].
>>>>>>>>>>
>>>>>>>>>> Good luck,
>>>>>>>>>>
>>>>>>>>>> Moritz
>>>>>>>>>>
>>>>>>>>>> [1]
>>>>>>>>>> https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300
>>>>>>>>>> [2] http://files.ettus.com/manual/page_usrp_e3x0.html
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> _______________________________________________
>>>>>>>>> USRP-users mailing list
>>>>>>>>> [email protected]
>>>>>>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>>>>>>>
>>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>
>>>>>
>>>>
>>>
>>> _______________________________________________
>>> USRP-users mailing list
>>> [email protected]
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>>
>>
>
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------------------------------
Message: 17
Date: Wed, 20 Apr 2016 13:42:04 +0200
From: Marcus M?ller <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] building a MIMO system without PPS signal
Message-ID: <[email protected]>
Content-Type: text/plain; charset="windows-1252"
Hi Ian,
In fact, I could even do stuff like triggering recording by using
setting the PPS source to "external", issuing a timed command far in the
future, and using set_time_next_pps to set the time of that command (or
anything after). Then, with a single signal edge, you can trigger streaming.
One of our customers asked how to do a triggered recording, so I had fun
taking one of these "big red buttons" that are usually used to serve as
emergency off buttons, and let that pull up the PPS line against a coin
cell. Hit the button to start recording samples :) Had I needed to do
this right, I'd probably have used a transistor to get the PPS edge as
steep as possible.
Cheers,
Marcus
On 04/20/2016 08:39 AM, Ian Buckley via USRP-users wrote:
> Its useful to bear in mind that a PPS signal is nothing other than a
> synchronization pulse in this type of system setup...it doesn't need
> to run continuously, nor do you need an extremely accurate absolute
> time value. All you really need is the 4 time counters in the USRP's
> you are using to count in synchronization. So it's entirely possible
> to be creative and use the 10MHz clock + small circuit of your own
> creation to generate a single logic transition on the PPS inputs
> allowing you to use a command like set_time_next_pps() to get align
> all the USRP's in time (relative to each other).
>
> -Ian
>
>
> On Tue, Apr 19, 2016 at 8:32 PM, Marcus D. Leech via USRP-users
> <[email protected] <mailto:[email protected]>> wrote:
>
> On 04/19/2016 11:10 PM, Yang Liu wrote:
>> Hi Marcus,
>>
>> Got it!
>>
>> Another question: how can I have access to multi_usrp in python?
>> I didn't find it in gnuradio.
>>
>> Thanks,
>> Yang
>>
> gr-uhd exposes multi-usrp.
>
> Best thing to do is to create a very simple GRC-based flow-graph
> with both devices in the same USRP source (and sink), and look at the
> generated code.
>
>
>> On Tue, Apr 19, 2016 at 9:29 PM, Marcus D. Leech
>> <[email protected] <mailto:[email protected]>> wrote:
>>
>> On 04/19/2016 09:00 PM, Yang Liu wrote:
>>> Hi Marcus,
>>>
>>> Thanks a lot for your help. I will try multi-usrp object!
>>>
>>> Since the PPS signal is not available so I don't use
>>> set_time_next_pps() or set_time_unknown_pps(). How should I
>>> evaluate the difference? I don't get this part.
>>>
>>> Thanks,
>>> Yang
>> You have two separate calls to set_time_now(), each calling
>> time.time() separately. That time.time() call is going to
>> return separate times.
>> You should evaluation the difference between:
>>
>> usrp1.set_time_now(time.time())
>> usrp2.set_time_now(time.time())
>>
>> and:
>>
>> t = time.time()
>>
>> usrp1.set_time_now(t)
>> usrp1.set_time_now(t)
>>
>>
>>
>>>
>>> On Tue, Apr 19, 2016 at 8:45 PM, Marcus D. Leech via
>>> USRP-users <[email protected]
>>> <mailto:[email protected]>> wrote:
>>>
>>> On 04/19/2016 07:43 PM, Yang Liu via USRP-users wrote:
>>>> Dear all,
>>>>
>>>> Now I am trying to build a 2x2 MIMO system using 4 USRP
>>>> N210s, and external 10MHz clock is used for frequency
>>>> synchronization. However, PPS signal is not available.
>>>>
>>>> the setup is: each USRP is connected to the PC directly
>>>> via ethernet cable and thus, all 4 USRPs (2 as
>>>> transmitters, 2 as receivers) are controlled by the
>>>> same host computer. 2 transmitting USRPs are
>>>> synchronized by one 10MHz clock, and 2 receiving USRPs
>>>> are synchronized by another 10MHz clock.
>>>>
>>>> In the beginning, I thought that our application
>>>> doesn't require time precision on every node, so
>>>> frequency synchronization suffices. However, the
>>>> experiment acted poorly. The bit error rate at the
>>>> receiver side was very large. I thought it should be
>>>> the problem with time synchronization (Since the code I
>>>> had works properly when the USRPs are synchronizied by
>>>> MIMO cables), so I followed some suggestions online to
>>>> achieve time synchronization at TX/RX:
>>>>
>>>> https://www.ruby-forum.com/topic/4409521
>>>> http://files.ettus.com/manual/page_sync.html
>>>>
>>>> here is the code for USRP N210 configuration at the
>>>> transmitter side (configuration at RX is very similar):
>>>> #################
>>>> transmitter
>>>> #################
>>>> self.usink0=uhd.usrp_sink(device_addr="addr0=192.168.10.2",
>>>> io_type=uhd.io_type.COMPLEX_FLOAT32, num_channels=1)
>>>> self.usink1=uhd.usrp_sink(device_addr="addr0=192.168.10.4",
>>>> io_type=uhd.io_type.COMPLEX_FLOAT32, num_channels=1)
>>>> self.usink0.set_clock_source("external")
>>>> self.usink1.set_clock_source("external")
>>>> self.usink0.set_time_now(uhd.time_spec_t(time.time()))
>>>> #set the time registers immediately
>>>> self.usink1.set_time_now(uhd.time_spec_t(time.time()))
>>>> self.usink0.set_samp_rate(self.samp_rate)
>>>> self.usink1.set_samp_rate(self.samp_rate)
>>>> self.usink0.set_gain(self.gain)
>>>> self.usink1.set_gain(self.gain)
>>>> self.usink0.set_antenna(self.antenna)
>>>> self.usink1.set_antenna(self.antenna)
>>>> future=time.time()+0.5
>>>> self.usink0.set_command_time(uhd.time_spec_t(future))
>>>> self.usink1.set_command_time(uhd.time_spec_t(future))
>>>> self.usink0.set_center_freq(self.freq)
>>>> self.usink1.set_center_freq(self.freq)
>>>> self.usink0.clear_command_time()
>>>> self.usink1.clear_command_time()
>>>> ################
>>>>
>>>>
>>>> After the changes, the performance improved, but still
>>>> not what I want. I am wondering whether it is possible
>>>> to implement a MIMO system for certain applications
>>>> without PPS signal especially when the application
>>>> doesn't require that much time precision. If yes, is
>>>> there anything else I can do to improve the current
>>>> system or is there anything wrong with my current
>>>> configuration?
>>>>
>>>> Thanks,
>>>> Yang
>>>>
>>>>
>>> You want a single multi-usrp object, not two separate
>>> ones. That will help.
>>>
>>> Also, you do a set_time_now() with two separate calls to
>>> time.time(), which will return two different times.
>>> It's likely better to use a single time,
>>> rather than two different ones. Since you're not
>>> using a set_time_next_pps() or set_time_unknown_pps(),
>>> you'll have to evaluate the
>>> difference between the two yourself, in your system.
>>>
>>>
>>>
>>>
>>> _______________________________________________
>>> USRP-users mailing list
>>> [email protected]
>>> <mailto:[email protected]>
>>>
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>>
>>
>>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected] <mailto:[email protected]>
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
>
>
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> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 18
Date: Wed, 20 Apr 2016 11:12:02 -0400
From: Sean Nowlan <[email protected]>
To: [email protected]
Subject: [USRP-users] b200mini: using GPIO pin for PPS reference
Message-ID:
<cagmpsnqkjh-js6atn10pvawkytk6igqh1yaeffbmonkcqoq...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
What modifications would need to be made to the b200mini FPGA source to
allow using a GPIO pin for a PPS input? We'd like to supply a GPSDO 10 MHz
reference to the SYNC port and a PPS signal to a GPIO pin to set the
time-of-day register with set_time_next_pps(). Basically we'd like to
duplicate the functionality available on N2x0 and B2x0 devices that have
dedicated 10 MHz and PPS reference ports.
Thanks,
Sean Nowlan
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Message: 19
Date: Wed, 20 Apr 2016 08:56:35 -0700
From: Jonathon Pendlum <[email protected]>
To: BHUSHAN PAWAR <[email protected]>
Cc: Nikos Balkanas <[email protected]>,
"[email protected]" <[email protected]>,
[email protected]
Subject: Re: [USRP-users] E310 : Interfacing ZynQ 7020 with AD 9361
RFIC and Filter Banks
Message-ID:
<CAGdo0uSF-b44ta+wKiRadtJPEyPPg=nzu7nz5moxht8ul2a...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi,
It looks like a problem with Vivado itself. Are you using one of the
support OSs (see
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug973-vivado-release-notes-install-license.pdf)?
Can you create a project with the GUI outside of our flow?
Jonathon
On Wed, Apr 20, 2016 at 2:45 AM, BHUSHAN PAWAR <[email protected]>
wrote:
> Dear Jonathon,
>
> Thanks for your reply. I followed your suggestion and and to build the
> project using command 'make E310 GUI=1'.
> It opened the GUI for Vivado, however before I could save the project
> there was an error and Vivado was closed automatically. Below are the lines
> from terminal also I am attaching the log file with this email,
>
> [pawa_bh@ohff24 e300]$ chmod u+x setupenv.sh
> [pawa_bh@ohff24 e300]$ . setupenv.sh
> Setting up X3x0 FPGA build environment (64-bit)...
> bash:
> /opt/Xilinx/Vivado_HLS/Vivado/2014.4/.settings64-Vivado_High_Level_Synthesis.sh:
> Datei oder Verzeichnis nicht gefunden
> - Vivado: Found (/opt/Xilinx/Vivado/Vivado/2014.4/bin)
>
> Environment successfully initialized.
> [pawa_bh@ohff24 e300]$ make E310 GUI=1
> make -f Makefile.e300.inc bin NAME=E310 ARCH=zynq
> PART_ID=xc7z020/clg484/-1 EXTRA_DEFS="E310"
> make[1]: Entering directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300'
> Vivado v2014.4 (64-bit)
>
> ****** Vivado v2014.4 (64-bit)
> **** SW Build 1071353 on Tue Nov 18 16:48:31 MST 2014
> **** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014
> ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
>
> start_gui
> Abnormal program termination (11)
> Please check
> '/home/pawa_bh/uhd/fpga-src/usrp3/top/e300/build-E310/hs_err_pid12758.log'
> for details
> make[1]: *** [bin] Fehler 139
> make[1]: Leaving directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300'
> make: *** [E310] Fehler 2
> [pawa_bh@ohff24 e300]$
>
>
> I tried building the project with only make E310 command and the bit file
> was generated without any error.
> Kindly help me to resolve this issue.
>
> *Thanks & Regards,*
>
> *Bhushan R.V. Pawar.*
> *(+49-17685263152 <%28%2B49-17685263152>)*
>
>
> On Wed, Apr 20, 2016 at 11:39 AM, BHUSHAN PAWAR <
> [email protected]> wrote:
>
>> Dear Jonathon,
>>
>> Thanks for your reply. I followed your suggestion and and to build the
>> project using command 'make E310 GUI=1'.
>> It opened the GUI for Vivado, however before I could save the project
>> there was an error and Vivado was closed automatically. Below are the lines
>> from terminal also I am attaching the log file with this email,
>>
>> [pawa_bh@ohff24 e300]$ chmod u+x setupenv.sh
>> [pawa_bh@ohff24 e300]$ . setupenv.sh
>> Setting up X3x0 FPGA build environment (64-bit)...
>> bash:
>> /opt/Xilinx/Vivado_HLS/Vivado/2014.4/.settings64-Vivado_High_Level_Synthesis.sh:
>> Datei oder Verzeichnis nicht gefunden
>> - Vivado: Found (/opt/Xilinx/Vivado/Vivado/2014.4/bin)
>>
>> Environment successfully initialized.
>> [pawa_bh@ohff24 e300]$ make E310 GUI=1
>> make -f Makefile.e300.inc bin NAME=E310 ARCH=zynq
>> PART_ID=xc7z020/clg484/-1 EXTRA_DEFS="E310"
>> make[1]: Entering directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300'
>> Vivado v2014.4 (64-bit)
>>
>> ****** Vivado v2014.4 (64-bit)
>> **** SW Build 1071353 on Tue Nov 18 16:48:31 MST 2014
>> **** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014
>> ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
>>
>> start_gui
>> Abnormal program termination (11)
>> Please check
>> '/home/pawa_bh/uhd/fpga-src/usrp3/top/e300/build-E310/hs_err_pid12758.log'
>> for details
>> make[1]: *** [bin] Fehler 139
>> make[1]: Leaving directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300'
>> make: *** [E310] Fehler 2
>> [pawa_bh@ohff24 e300]$
>>
>>
>> I tried building the project with only make E310 command and the bit file
>> was generated without any error.
>> Kindly help me to resolve this issue.
>>
>>
>> *Thanks & Regards,*
>>
>> *Bhushan R.V. Pawar.*
>>
>>
>> On Mon, Feb 15, 2016 at 11:14 PM, Jonathon Pendlum <
>> [email protected]> wrote:
>>
>>> Hi Pawar,
>>>
>>> It looks like you created a Vivado project file and then manually
>>> imported source files. I would suggest instead running make with GUI=1,
>>> i.e. make GUI=1 E310. This will load the Vivado GUI and you can save a
>>> project file from there (File->Save Project As...).
>>>
>>>
>>>
>>> Jonathon
>>>
>>> On Mon, Feb 15, 2016 at 8:05 AM, Nikos Balkanas via USRP-users <
>>> [email protected]> wrote:
>>>
>>>> Hi,
>>>>
>>>> Did you followed the Makefile procedure indicated by James? What target
>>>> did you build?
>>>>
>>>> Nikos
>>>>
>>>> On Mon, Feb 15, 2016 at 5:26 PM, BHUSHAN PAWAR <
>>>> [email protected]> wrote:
>>>>
>>>>> Errors:
>>>>>
>>>>> [Synthv8-448] named port connection 'GPIO_I' does not exist for
>>>>> instance 'inst_processing_system7' of module 'processing_system7_1'
>>>>> [e3xx_ps.v.263]
>>>>> (85 more like this)
>>>>>
>>>>> [Synthv8-285] failed synthesizing module 'axi4_fifo_512x64'
>>>>> [axi4_fifo_512x64_stub.v.7]
>>>>> (2 more like this)
>>>>>
>>>>> *Thanks & Regards,*
>>>>>
>>>>> *Bhushan R.V. Pawar.*
>>>>> *(+49-17685263152 <%28%2B49-17685263152>)*
>>>>>
>>>>>
>>>>> On Mon, Feb 15, 2016 at 4:08 PM, BHUSHAN PAWAR <
>>>>> [email protected]> wrote:
>>>>>
>>>>>> Hi all,
>>>>>>
>>>>>> I am using the source code from Github usrp3/top/e300 and trying to
>>>>>> synthesize the code. However, I am getting these errors. Kindly help.
>>>>>>
>>>>>> [image: Inline image 2][image: Inline image 1]
>>>>>>
>>>>>>
>>>>>> *Thanks !!*
>>>>>>
>>>>>>
>>>>>> On Mon, Feb 15, 2016 at 1:22 PM, Nikos Balkanas <[email protected]>
>>>>>> wrote:
>>>>>>
>>>>>>> Hi Pawar,
>>>>>>>
>>>>>>> The FPGA sources are to modify the FPGA. The FPGA is larger than the
>>>>>>> image it currently holds. Many people use it to add aditional filters,
>>>>>>> FFTs, etc.
>>>>>>> Adding on top of what already exists and is needed for correct
>>>>>>> functionality...But you need to know Vivado for that. Check also RFNOC,
>>>>>>> it
>>>>>>> may be easier:)
>>>>>>>
>>>>>>> PS: Plz keep discussion in group, so that others may benefit as
>>>>>>> well...
>>>>>>>
>>>>>>> HTH,
>>>>>>> Nikos
>>>>>>>
>>>>>>> On Mon, Feb 15, 2016 at 2:11 PM, BHUSHAN PAWAR <
>>>>>>> [email protected]> wrote:
>>>>>>>
>>>>>>>> Hi Nikos,
>>>>>>>>
>>>>>>>> Thanks for the reply.
>>>>>>>>
>>>>>>>> Then can you explain me what is the real use of the FPGA code on
>>>>>>>> usrp3/top/e300 subdirectory on github.
>>>>>>>>
>>>>>>>> How can I use this code to get started?
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> *Thanks & Regards,*
>>>>>>>>
>>>>>>>> *Bhushan R.V. Pawar.*
>>>>>>>>
>>>>>>>>
>>>>>>>> On Mon, Feb 15, 2016 at 12:06 PM, Nikos Balkanas <
>>>>>>>> [email protected]> wrote:
>>>>>>>>
>>>>>>>>> Hi,
>>>>>>>>>
>>>>>>>>> Have you also tried vivado forums? They can help more than what we
>>>>>>>>> can here...
>>>>>>>>> Plz post your errors. Recently started on vivado myself, and the
>>>>>>>>> only errors I got were from licensing issues for my FPGA.
>>>>>>>>> I have an X300
>>>>>>>>>
>>>>>>>>> HTH,
>>>>>>>>> Nikos
>>>>>>>>>
>>>>>>>>> On Mon, Feb 15, 2016 at 12:54 PM, BHUSHAN PAWAR via USRP-users <
>>>>>>>>> [email protected]> wrote:
>>>>>>>>>
>>>>>>>>>> Dear Moritz,
>>>>>>>>>>
>>>>>>>>>> Thank you for the reply.
>>>>>>>>>>
>>>>>>>>>> I want to use E310 as multi channel transmitter and receiver and
>>>>>>>>>> want to test it using signal generator and oscilloscope.
>>>>>>>>>>
>>>>>>>>>> I tried to import the code from usrp3/top/e300 subdirectory into
>>>>>>>>>> Vivado 2015.4 but it is giving many errors when I try to synthesize
>>>>>>>>>> it.
>>>>>>>>>>
>>>>>>>>>> Can you explain me step by step, how to work with E310.
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> *Thanks !!*
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer <
>>>>>>>>>> [email protected]> wrote:
>>>>>>>>>>
>>>>>>>>>>> Hi Bhushan,
>>>>>>>>>>>
>>>>>>>>>>> On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users
>>>>>>>>>>> <[email protected]> wrote:
>>>>>>>>>>> > Hello,
>>>>>>>>>>> >
>>>>>>>>>>> > I am trying to build multi channel transmitter and receiver
>>>>>>>>>>> using USRP E310.
>>>>>>>>>>>
>>>>>>>>>>> all our code for E310 is open-source. Feel free to peruse our
>>>>>>>>>>> github.
>>>>>>>>>>> On the FPGA side you might wanna look at the usrp3/top/e300
>>>>>>>>>>> subdirectory [1].
>>>>>>>>>>>
>>>>>>>>>>> If you let us know what exactly you're trying to do, people can
>>>>>>>>>>> help
>>>>>>>>>>> you out easier.
>>>>>>>>>>> > However I am new to FPGA programming, hence I am facing a lot
>>>>>>>>>>> of challenges
>>>>>>>>>>> > in interfacing ZynQ board with the transceiver and filter
>>>>>>>>>>> banks in Vivado
>>>>>>>>>>> > 2015.4.
>>>>>>>>>>> > Is to possible to get few demo projects which might help me to
>>>>>>>>>>> understand
>>>>>>>>>>> > the data flow in the simple transmitter and receiver
>>>>>>>>>>> application? Kindly
>>>>>>>>>>> > share few useful documents which will help me to understand
>>>>>>>>>>> the above
>>>>>>>>>>> > problem.
>>>>>>>>>>>
>>>>>>>>>>> Again, all our code for E310 is open source (apart from Xilinx
>>>>>>>>>>> IP).
>>>>>>>>>>> Feel free to dig through the code.
>>>>>>>>>>> The filter bank settings are documented in the UHD manual [2].
>>>>>>>>>>>
>>>>>>>>>>> Good luck,
>>>>>>>>>>>
>>>>>>>>>>> Moritz
>>>>>>>>>>>
>>>>>>>>>>> [1]
>>>>>>>>>>> https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300
>>>>>>>>>>> [2] http://files.ettus.com/manual/page_usrp_e3x0.html
>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> _______________________________________________
>>>>>>>>>> USRP-users mailing list
>>>>>>>>>> [email protected]
>>>>>>>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>
>>>>>
>>>>
>>>> _______________________________________________
>>>> USRP-users mailing list
>>>> [email protected]
>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>>
>>>>
>>>
>>
>
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