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Today's Topics:
1. [RFNoC] Announcing tutorials at GRCon (Martin Braun)
2. USRPN200_Time Delay between RX2_TX/RX? (Mariam Musavi)
3. Re: Creating a custom RFNoC Block (Jonathon Pendlum)
4. UHD error (john liu)
5. Re: UHD error (Marcus D. Leech)
6. Re: UHD error (liu Jong)
7. Re: UHD error (Marcus D. Leech)
8. Suggestions For High End Laptop (Sumit Kumar)
9. More B205 FPGA Acceleration Questions (Mark Napier)
10. Re: Suggestions For High End Laptop (Steven Knudsen)
----------------------------------------------------------------------
Message: 1
Date: Wed, 29 Jun 2016 09:18:52 -0700
From: Martin Braun <[email protected]>
To: "[email protected]" <[email protected]>,
"'[email protected]'" <[email protected]>
Subject: [USRP-users] [RFNoC] Announcing tutorials at GRCon
Message-ID: <[email protected]>
Content-Type: text/plain; charset=utf-8
Hi everyone,
we're very happy to announce that we will be doing another set of
tutorials at this year's GRCon. The tutorial is free, and will happen on
the new user's day at GRCon (Mon, September 12th), *but* it requires
that you purchase a ticket for the new user's day, should you have not
already done so.
There's a limited headcount, so if you want to attend, please head over
to the registration page and get your tutorial ticket (and, if
necessary, your new user's day ticket):
https://www.eventbrite.com/e/gnu-radio-conference-2016-tickets-24257809762
Note: If you register for the tutorial without having registered for the
new user's day, we might have to un-register you and give the seat to
other participants, should there be a waitlist. I therefore recommend
you get your new user's day ticket at the same time as the RFNoC
tutorial ticket, should you require one.
We will follow up with details on the tutorial, but it will be a
hands-on introduction to RFNoC development. Participants will create
their own block and run it on an embedded device.
We will provide all the hardware and a bootable USB drive containing all
the required software. We might also provide laptops, but that remains
to be figured out.
If you're already a somewhat experienced user of RFNoC, you most likely
won't get all that much out of the tutorial, since we'll be focussing on
getting people started. A large portion of Ettus R&D will be at GRCon
and you can grab us and ask us questions outside of the tutorial, too.
Cheers,
Martin
------------------------------
Message: 2
Date: Wed, 29 Jun 2016 21:46:31 +0500
From: Mariam Musavi <[email protected]>
To: [email protected]
Subject: [USRP-users] USRPN200_Time Delay between RX2_TX/RX?
Message-ID:
<caan2pfo4xcqtmsijoyspmafly5mzretqc3noug0ouz8t0dj...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Greetings all USRP2 Users!
I am using USRPN200 has 2 antenna interfaces. One is TX/RX which is
normally used for transmission and second RX2 which is assigned for
reception purpose. modulation scheme is gmsk at transmitter and gmsk at
receiver. I am also aware that if TX/RX interface is active and it uses one
frequency (lets say freq1=828 MHz) and when RX2 interface is active it must
uses another frequency than the frequency assigned to TX/RX (say freq2=836
MHz). My question is,
1. How can i introduce user defined time delay between reception at
freq2 and transmission at freq1.
2. Does that mean introducing time delay may lead to introducing buffer?
--
Regards
Syed Mariam
GRA & M.Sc. Candidate
Wireless Network & Protocol Research Lab MIMOS,
Faculty of Science and Technology, Sun-U Malaysia and
Lancaster University UK (dual program)
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Message: 3
Date: Wed, 29 Jun 2016 14:29:39 -0500
From: Jonathon Pendlum <[email protected]>
To: "El Ouni, Naceur (IntlAssoc)" <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] Creating a custom RFNoC Block
Message-ID:
<CAGdo0uQQ4QTUOw=le_whi2yajwzvah7yxr0jn4o8xktwq2g...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi Naceur,
I find it easiest to mark which nets you want to chipscope using the
Verilog pragma (* dont_touch = "true", mark_debug = "true" *). After you
have marked the nets, you can instantiate an ILA via the GUI using "Setup
Debug" under "Synthesis".
Jonathon
On Mon, Jun 27, 2016 at 2:08 PM, El Ouni, Naceur (IntlAssoc) via USRP-users
<[email protected]> wrote:
> Hi Martin,
>
>
>
> > I think I'm missing something -- how are you expecting the $display()
> command to display? Do you have some debugging setup? Is there some kind of
> chipscope/ILA involved?
>
> Could you direct me to an example using chipscope/ILA or any resource on
> the matter because I am only following the RFNOC tutorial file and the
> source code itself.
>
> Following a Xilinx Tutorial of Vivado ILA, I have to instantiate an ILA IP
> and plug it in the design.
>
> I am doing this for the first time so help is much appreciated. I don?t
> know if I should use the monitor type AXI, since RFNOC is based on AXI
> standard.
>
>
>
>
>
> Next after the IP is generated, how to integrate it in the design ? Is
> there an RFNOC Vivado sample project that has debug features to follow ? I
> am going in the right direction ?
>
>
>
>
>
>
>
> > Is data flowing through your blocks? What's happening?
>
> Re the data flow: I am not following what?s happening in between the
> blocks. (How to monitor that ?).
>
> I generated an all-ones 256 vectors file in matlab that I use in this
> flowgraph and
>
> I am looking at the bin_aggr output (at file sink) expecting a file of
> vectors of 5s instead of ones: 50 bins of value 5 each and 3 vectors on
> each side of 0 value.
>
>
>
> > Can you give us more info on your failure modes?
>
> When reading the file in Matlab (or even Hexdump in Linux) I get a file of
> all zeros.
>
>
>
>
>
> Thanks and Regards,
>
>
>
> Naceur El Ouni
>
> NIST - Wireless Networks Division (673)
>
> 100 Bureau Dr. Building 222-A218
>
> Gaithersburg, MD 20899
>
> (301) 975-3353
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 4
Date: Thu, 30 Jun 2016 09:44:51 +0800
From: john liu <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] UHD error
Message-ID:
<CAF6NnTL_fEfXRD140TXEAQDh=qvsmwdb-yrqx-vsm1d6fi3...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Dear all,
we record signal with B200. Below is our GRC set.
[image: Inline image 1]
Recording last about 10s,then uhd error output:
UHD Error:
The receive packet handler caught an exception.
ValueError: bad vrt header or packet fragment
gr::log :WARN: gr uhd usrp source0 - USRP Source Block caught rx error
code: 15
DO
I looked for solution on mail list?but can not find answer.
thank you for your help.
best regards
John
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Message: 5
Date: Wed, 29 Jun 2016 21:50:45 -0400
From: "Marcus D. Leech" <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] UHD error
Message-ID: <[email protected]>
Content-Type: text/plain; charset="utf-8"; Format="flowed"
On 06/29/2016 09:44 PM, john liu via USRP-users wrote:
> Dear all,
> we record signal with B200. Below is our GRC set.
> Inline image 1
> Recording last about 10s,then uhd error output:
> UHD Error:
> The receive packet handler caught an exception.
> ValueError: bad vrt header or packet fragment
> gr::log :WARN: gr uhd usrp source0 - USRP Source Block caught rx error
> code: 15
> DO
> I looked for solution on mail list?but can not find answer.
> thank you for your help.
> best regards
> John
>
>
What type of computer? What type of storage device is this being
written to?
I notice both a 'D' and 'O' in the output, indicating some severe
lossage on the USB channel.
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Message: 6
Date: Thu, 30 Jun 2016 10:58:35 +0800
From: liu Jong <[email protected]>
To: "Marcus D. Leech" <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] UHD error
Message-ID:
<CAEui2n0q7zaJ-8h+Y9a3+PAeYaeaXcOLNFGbQWYPdrUSC=r...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Marcus,
thank you for your reply.
here is the type of PC.
Thinkpad T450
i7
8G Memory
500G SSD
USB3.0
before today,the recording is normal.
i tred again,and when the size of recording file reach 3GB?the uhd error
output.
2016-06-30 9:50 GMT+08:00 Marcus D. Leech via USRP-users <
[email protected]>:
> On 06/29/2016 09:44 PM, john liu via USRP-users wrote:
>
> Dear all,
> we record signal with B200. Below is our GRC set.
> [image: Inline image 1]
> Recording last about 10s,then uhd error output:
> UHD Error:
> The receive packet handler caught an exception.
> ValueError: bad vrt header or packet fragment
> gr::log :WARN: gr uhd usrp source0 - USRP Source Block caught rx error
> code: 15
> DO
> I looked for solution on mail list?but can not find answer.
> thank you for your help.
> best regards
> John
>
>
> What type of computer? What type of storage device is this being written
> to?
>
> I notice both a 'D' and 'O' in the output, indicating some severe lossage
> on the USB channel.
>
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 7
Date: Wed, 29 Jun 2016 23:08:01 -0400
From: "Marcus D. Leech" <[email protected]>
To: liu Jong <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] UHD error
Message-ID: <[email protected]>
Content-Type: text/plain; charset="utf-8"; Format="flowed"
On 06/29/2016 10:58 PM, liu Jong wrote:
> Marcus,
> thank you for your reply.
>
> here is the type of PC.
> Thinkpad T450
> i7
> 8G Memory
> 500G SSD
> USB3.0
>
> before today,the recording is normal.
> i tred again,and when the size of recording file reach 3GB?the uhd
> error output.
The data rate should be about 16MB/second, so 3GB is about 3minutes of data.
What's likely going on is that your operating system is doing a
write-back to the hard-disk, and that is causing all disk I/O to slow
down to the
point where the entire pipeline stalls.
This isn't, per se, a problem with Gnu Radio or UHD, but rather in
operating system parameters related to disk I/O, and cache write-back.
You'll have to look into tuning the cache write-back parameters on your
system. Also, the SSD may not be that fast. So even changing your
write-back parameters may not help.
>
> 2016-06-30 9:50 GMT+08:00 Marcus D. Leech via USRP-users
> <[email protected] <mailto:[email protected]>>:
>
> On 06/29/2016 09:44 PM, john liu via USRP-users wrote:
>> Dear all,
>> we record signal with B200. Below is our GRC set.
>> Inline image 1
>> Recording last about 10s,then uhd error output:
>> UHD Error:
>> The receive packet handler caught an exception.
>> ValueError: bad vrt header or packet fragment
>> gr::log :WARN: gr uhd usrp source0 - USRP Source Block caught rx
>> error code: 15
>> DO
>> I looked for solution on mail list?but can not find answer.
>> thank you for your help.
>> best regards
>> John
>>
>>
> What type of computer? What type of storage device is this being
> written to?
>
> I notice both a 'D' and 'O' in the output, indicating some severe
> lossage on the USB channel.
>
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected] <mailto:[email protected]>
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 8
Date: Thu, 30 Jun 2016 11:30:47 +0200
From: Sumit Kumar <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] Suggestions For High End Laptop
Message-ID:
<CAOExtcTrcA3RWmrJkmrnDDLkhyhLEWx7+q=rlhfovzdsa0e...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hello
I am about to buy a laptop which will be used with USRP B210 i.e. USB 3.0
Suggestions for high end laptops ?
Budget approx : 2000 Euro
TIA
--
--
Sumit kumar
Doctoral Student, UPMC
Eurecom, BIOT
France
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Message: 9
Date: Thu, 30 Jun 2016 09:13:54 -0400
From: Mark Napier <[email protected]>
To: [email protected], [email protected]
Subject: [USRP-users] More B205 FPGA Acceleration Questions
Message-ID:
<CAFS2mBcUEbEVeK1ukM-q9b-9RrKVFyLZLJD-dWMS9WaqfP=2...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hey Austin,
I'm working on a project using a B205 and very similar processing. I've
tossed the idea of using any of the underlying framing from the UHD, its
just too damn hard for me to figure out quickly and I have a tight
schedule. I'm a hardware/DSP guy and the learning curve on this software
stack is very steep.
Instead I took Martin's advice and am working on something simple. Use
everything the way it is. Put all our processing in the legacy radio
block. Configure the the B205 using the UHD to get the radio clock rate
and decimation rate we want. Do all the base band processing in hardware.
At the end, the data I want to output even with all the status reporting is
less than the configured sample rate from the B205 to the UHD. Great.
Configure the "Over the Wire" and output data for raw fixed point 16-bit
I/Q; that is 32-bits per sample. Make up my own frame just using the
"samples" as a raw transport. I like a unique word followed by an
incrementing counter and then a simple checksum at the end of the frame. A
simple repetitive structure that is easy for software to lock onto and
parse.
Save anything harder for when I have more time (maybe never.)
I would very much like to hear how you do your custom register writes and
reads and how you wind up getting your data in and out.
Cheers,
Mark Napier
------------------------------
>
> Message: 2
> Date: Tue, 28 Jun 2016 11:02:14 -0600
> From: Austin Anderson <[email protected]>
> To: "[email protected]" <[email protected]>
> Subject: [USRP-users] More B205 FPGA Acceleration Questions
> Message-ID:
> <CAF30z8d6aZr9GwkMotEZRqGbkk4EnTnZKnMGgz8ky7csSPMG=
> [email protected]>
> Content-Type: text/plain; charset="utf-8"
>
> Hi All,
> I have a couple follow up questions about using the FPGA on the B205. I'm
> planning on replacing the DUC/DDC with my own processing cores and using
> the user setting registers for configuration/control.
>
> 1. I understand how to turn on the user registers and what values I'd need
> to write where to do what I want. What I'm unclear on is how to access this
> from the host software. I can see in:
>
> uhd/host/lib/usrb/b200/b200_impl.cpp
>
> where peek/poke calls exist that I can use. I've been working with the
> example at:
>
> uhd/host/examples/rx_samples_to_file.cpp
>
> If I add a new method to the b200_impl class, is there a straightforward
> way to call that from the usrp object created in that example? Is adding a
> new method the recommended approach?
>
> 2. The most basic processing I'd like to do is a fixed point FFT. I'd like
> to synch up the framing of the FFT in the FPGA fabric with the framing of
> the data on the host side. The FFT's framing can be synch'd up by pulsing a
> reset signal. Does the host-side pulse a reset to the FPGA fabric to start
> a data transfer? If that's the case, syncing the framing should be pretty
> easy.
>
> Thanks,
> -Austin
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Message: 10
Date: Thu, 30 Jun 2016 09:15:51 -0600
From: Steven Knudsen <[email protected]>
To: Sumit Kumar <[email protected]>
Cc: USRP-users <[email protected]>
Subject: Re: [USRP-users] Suggestions For High End Laptop
Message-ID: <[email protected]>
Content-Type: text/plain; charset="utf-8"
I just bought an MSI GE62 6QD Apache Pro. Took a bit of work to get Linux Mint
17.3 and a 4.6 kernel working, but I can confirm that the USB 3 is compatible
with a B200mini (and I assume other Bxx).
It is pretty powerful and more than enough for the GR designs I make.
It?s the Steel series, so nicely built. Does not run hot and weight is okay.
Hope this helps,
steven
> On Jun 30, 2016, at 03:30 AM, Sumit Kumar via USRP-users
> <[email protected]> wrote:
>
> Hello
>
> I am about to buy a laptop which will be used with USRP B210 i.e. USB 3.0
>
> Suggestions for high end laptops ?
>
> Budget approx : 2000 Euro
>
> TIA
>
> --
> --
> Sumit kumar
> Doctoral Student, UPMC
> Eurecom, BIOT
> France
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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