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Today's Topics:
1. Re: How to add interrupts on E310's Linux system (Weidong Wang)
2. USRP B200 starter kit for sale (Ch'Gans)
3. ??: Re:usrp-n210:Expected FPGA compatibility number 10,but
got 16 (???)
4. ??? Problem using B210 with two different RX frequency
(=?gb18030?B?1cXDyA==?=)
5. Xilinx ISE for B210 (Vipin Sharma)
6. Re: Reg : nsamps_per_buff in UHD (Sumit Kumar)
7. Format of complex data saved thru uhd_rx_cfile. Is it Q15 ?
(Sumit Kumar)
8. Re: Xilinx ISE for B210 (Sumit Kumar)
9. Re: How to add interrupts on E310's Linux system (Marcus M?ller)
10. Re: Xilinx ISE for B210 (James Humphries)
11. Re: How to add interrupts on E310's Linux system (Weidong Wang)
12. Re: How to add interrupts on E310's Linux system (Marcus M?ller)
----------------------------------------------------------------------
Message: 1
Date: Mon, 11 Jul 2016 03:36:16 +0000
From: Weidong Wang <wwd_u...@hotmail.com>
To: Moritz Fischer <moritz.fisc...@ettus.com>
Cc: "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com>,
"Landry, Rene Jr." <renejr.lan...@etsmtl.ca>, J?r?me Lecl?re
<jerome.lecl...@lassena.etsmtl.ca>
Subject: Re: [USRP-users] How to add interrupts on E310's Linux system
Message-ID:
<bl2pr03mb4666d09f2321da183d04a53f0...@bl2pr03mb466.namprd03.prod.outlook.com>
Content-Type: text/plain; charset="utf-8"
Hi Moritz,
Thanks again for your replies.
I am migrating an existed GNSS system into E310. So I need to add at least 13
interrupts into E310's RFNOC system.
I did some searches from Internet, and I fond this blog:
<http://svenand.blogdrive.com/archive/203.html#.V4MP0O1VK1E>
http://svenand.blogdrive.com/archive/203.html#.V4MP0O1VK1E
The author of this blog explained how to add uio into zynq linux system using
the petalinux, linux kernel and the device tree definition file system.dts.
I want to know if I can use the same procedures to add the interrupts? Should I
use yocto instead of petalinux, or together? And what's the linux kernel's
version of E310 and where I can find the device tree definition file of E310?
Best regards,
[cid:part2.00040309.02040909@hotmail.com]<http://etsmtl.ca>
[cid:part4.06080303.06060201@hotmail.com]<http://lassena.etsmtl.ca>
[cid:part6.05000001.06050900@hotmail.com]<http://twitter.com/lassenaets>
[cid:part8.05020300.07020808@hotmail.com]
<http://www.linkedin.com/company/laboratoire-de-recherche-lassena>
[cid:part10.09060304.05030509@hotmail.com]
<http://www.facebook.com/lassena.etsmtl.ca> Weidong WANG | ?tudiant ?
la Ma?trise
Laboratoire LASSENA
?cole de technologie sup?rieure | 1100, rue Notre-Dame Ouest |
Montr?al (Qc) Canada | H3C 1K3
Tel.: 514 396-8800, poste 7930 | Bureau : A-2568 |
www.etsmtl.ca<http://www.etsmtl.ca>
Email : <mailto:weidong.w...@lassena.etsmtl.ca>
weidong.w...@lassena.etsmtl.ca<mailto:weidong.w...@lassena.etsmtl.ca>
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On 16-07-06 01:56 PM, Moritz Fischer wrote:
Hi Weidong,
On Tue, Jul 5, 2016 at 12:52 PM, Weidong Wang via USRP-users
<usrp-users@lists.ettus.com><mailto:usrp-users@lists.ettus.com> wrote:
Hi all,
I want to create a simple CE using RFNOC to generate an interrupt and send
it to the ARM cpu.
1. Could I add this interrupt signal directly to the signal "IRQ_F2P" in
e310.v?
In e310.v line 415, we have :
// Misc interrupts, GPIO, clk
.IRQ_F2P({12'h0, pmu_irq, button_release_irq, button_press_irq,
stream_irq}),
You can either use one of the remaining IRQ lines or turn a GPIO into
an IRQ source.
2. How could I add it in linux system? I fond some topics about it for the
regular linux systems, but it seems not useful for the system on E310.
At what level do you want to deal with the IRQ? Kernel? Userland? UHD
or RFNoC for that
matter currently doesn't have low level primitives do deal with
interrupts, nothing prevents you
from using techniques like UIO or writing a kernel module to receive
interrupts, though.
Moritz
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------------------------------
Message: 2
Date: Sun, 10 Jul 2016 13:11:59 +1200
From: "Ch'Gans" <chg...@gna.org>
To: usrp-users@lists.ettus.com
Subject: [USRP-users] USRP B200 starter kit for sale
Message-ID:
<cabxguti69rf5ctjbdqvdfrk+vmz9cyfy2_abfqut7dxbfzf...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi all,
I'm selling my USRP B200 kit which I'm not using anymore, from the invoice:
- 1 x USRP B200 SDR kit, 70MHz-6GHz with USB3 cable,
seehttps://www.ettus.com/product/details/UB200-KIT
- 2 x LP0965 Log Periodic PCB antenna wideband, 850 MHz-2.6GHz,
seehttps://www.ettus.com/product/details/LP0965
- 4 x SMA to SMA cable assembly, 0.5m,
seehttps://www.ettus.com/product/details/SMA-SMA
I have the original invoice and packaging. The kit is like new and the
B200 runs original firmware.
The current value of the kit for a New Zealander is: [1170 NZ$ + 2x80
NZ$ + 4x55 NZ$] + GST = 1550 NZ$ + GST = 1782.5 NZ$
I'm now selling the whole kit for 1000 NZ$ + shipping cost
FYI, as of 10th of July 2016, 1000NZD = 661.16 EUR = 730.62 USD
Expect ca. 30 NZ$ for worldwide shipping, and ca. 15 NZ$ for NZ/AUS
Shipping. Will provide you the exact cost if you tell me how you want
to arrange for shipping/delivery.
Happy hacking,
Chris
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Message: 3
Date: Sun, 10 Jul 2016 21:24:31 +0800
From: ??? <wang...@outlook.com>
To: <usrp-users@lists.ettus.com>
Subject: [USRP-users] ??: Re:usrp-n210:Expected FPGA compatibility
number 10,but got 16
Message-ID: <blu404-eas2744893f4677171e4003448a3...@phx.gbl>
Content-Type: text/plain; charset="gb2312"
???: ??? [mailto:wang...@outlook.com]
????: 2016?7?10? 16:38
???: marcus.muel...@ettus.com
??: RE:Re:usrp-n210:Expected FPGA compatibility number 10,but got 16
Dear marcus.mueler,
I check my network card by use "lspci|grep -i ether", the network
card message is presented in terminal as : Ethernet controller: Intel
Corporation 82567LM Gigabit Network Connection (rev 03).
The network capture by wireshark is in attachment.
In addition, I update my UHD and images to UHD_003.009.004-release.
But the problem is still present.
Thank you very very much for you to take time to help me resolute
the problem!
sincerely
wangerw
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------------------------------
Message: 4
Date: Sat, 9 Jul 2016 19:21:20 +0800
From: "=?gb18030?B?1cXDyA==?=" <leon...@qq.com>
To: "=?gb18030?B?TWFyY3VzIE2ouWxsZXI=?=" <marcus.muel...@ettus.com>,
"=?gb18030?B?dXNycC11c2Vycw==?=" <usrp-users@lists.ettus.com>
Subject: [USRP-users] ??? Problem using B210 with two different RX
frequency
Message-ID: <tencent_4684cb193c2f5f1d65f69...@qq.com>
Content-Type: text/plain; charset="gb18030"
Hi Marcus!
Thanks for your reply!
The parameter "master_clock_rate" for B210 means the sampling rate of the
ADC in AD9361, right? Do you means that the 2 RX channels share a total rate of
61.44Msps? I noticed that when using 2 channels the UHD set the highest
master_clock_rate to 30.72MHz. I thought it's just a consideration for USB 3.0
transmission. So I simply disabled the "enforce_tick_rate_limits" function in
b200_impl.cc in UHD source code and set the "tune" function in ad9361_ctrl.cpp
to a constant (e.g 940MHz) and compiled the UHD again. Then I can set the
master_clock_rate higher. For example, I set master_clock_rate to 40MHz and
sampling rate to 4Msps. I can see messages printed by UHD said the LO, the
master clock rate, the decimation rate and the sampling rate were set as I
expected. When I changed the center frequency of 2 channels, I can also see the
DSP DDC works well. Also the FFT results showed the GSM downlink signals
correctly. This just didn't work when the master_clock_rate set higher than
45MHz. I noticed that the noise floor raised about 20dB. It seemed that the
GSM signal is covered.
I just took a simply look at the AD9361 datasheet and I didn't find the
description for "2 channels share a total rate of 61.44Msps". Could you show me
where the description is? If this is the reason I failed, what should I do?
My application: uplink 885--890MHz & downlink 930 -- 935MHz.
Thank you!
Zhangmeng
------------------ ???? ------------------
???: "Marcus M?ller via USRP-users";<usrp-users@lists.ettus.com>;
????: 2016?7?9?(???) ??5:30
???: "usrp-users"<usrp-users@lists.ettus.com>;
??: Re: [USRP-users] Problem using B210 with two different RX frequency
Hi Zhangmeng,
I disabled the limit of sampling rate in UHD while using two RXs.
What exactly did you change? As far as I know, there's only one limit in
there ? and that's the hardware limitation of the AD9361 chip, which
can't use full rates in dual channel configuration.
Then I set the master_clock_rate to 32MHz - 44MHz and it works
fine Last time I tried, the maximum master clock rate for two channels
is 30.72 MHz, as dictated by by the maximum data clock frequency of
the AD9361, which is 61.44 MHz, and has to be shared between the two
channels. So, in fact, I'm a little surprised you say it works fine!
When I set master_clock_rate to 32MHz or higher, sampling rate of data
processing on PC is set to 2M to 4Msps. Are you sure you've
actually set a master clock rate of > 30.72 MHz? Is it possible that UHD
automatically used a different rate?
So, I'd like to fully understand the situation here:
We're talking about E-GSM 900, with uplink at 880.0 ? 915.0 MHz
and downlink at 925.0 ? 960.0, right?
Best regards,
Marcus
On 08.07.2016 05:56, ?? via USRP-users wrote:
Hi!
Recently I tried to use B210 to receive both uplink and
downlink channels of GSM 900. I noticed that the two RX channels in
AD9361 share one LO. So I have to set a high sampling rate (at least
45Msps) and do DDC and decimation using FPGA. I disabled the limit of
sampling rate in UHD while using two RXs. Then I set the
master_clock_rate to 32MHz - 44MHz and it works fine. But when I
set the master_clock_rate higher than 45MHz I got nothing but
noise. It doesn't works when the rate is higher than 45MHz. What's
wrong with that? Or is there other way to receive both up&downlink
of GSM signals using B210?
PS: When I set master_clock_rate to 32MHz or higher,
sampling rate of data processing on PC is set to 2M to 4Msps.
Best wishes!
Zhangmeng
_______________________________________________ USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 5
Date: Sat, 9 Jul 2016 19:40:55 -0700
From: Vipin Sharma <vipinsha...@photonpace.com>
To: usrp-users@lists.ettus.com
Subject: [USRP-users] Xilinx ISE for B210
Message-ID: <347a3525-0e85-414d-9691-8583aebf3...@photonpace.com>
Content-Type: text/plain; charset=us-ascii
Hi,
I would like to modify the default FPGA image by customizing the default
Verilog source code. I assume I will need Xilinx ISE to achieve this. Is this
going to be free or a license purchase is required from Xilinx?
Thanks,
Vipin
------------------------------
Message: 6
Date: Mon, 11 Jul 2016 10:27:26 +0200
From: Sumit Kumar <cog...@gmail.com>
To: Martin Braun <martin.br...@ettus.com>
Cc: "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] Reg : nsamps_per_buff in UHD
Message-ID:
<CAOExtcQnyouV1E=fmFrqh=o_frhtn+wbo3anh-ngm1zswgf...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Ok... I got it. Actually my code had an if else based on the number of
samples returned and it was breaking frequently. Now I am setting another
criterion.
On Fri, Jul 8, 2016 at 2:05 AM, Martin Braun via USRP-users <
usrp-users@lists.ettus.com> wrote:
> That's one reason, another would be if you have an overrun. There's no
> strong guarantee on the number of samples recv() will return.
>
> M
>
> On 07/07/2016 08:25 AM, Dave NotTelling via USRP-users wrote:
> > The first thing that comes to mind is the timeout getting hit so it only
> > returns up to the number of samples it got up to that point.
> >
> > On Thu, Jul 7, 2016 at 7:18 AM, Sumit Kumar via USRP-users
> > <usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>> wrote:
> >
> > *I am using UHD_003.009.002-0-gf18abe54*
> >
> > Is it common that the receive streamer sometimes returns lesser
> > number of samples than we ask.
> >
> > I have set nsamps_per_buff = 4096
> >
> > but sometimes the samples received are less than 4096.
> >
> > What can be the reason for that ?
> >
> > Sumit
> >
> >
> >
> > _______________________________________________
> > USRP-users mailing list
> > USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> >
> >
> >
> >
> > _______________________________________________
> > USRP-users mailing list
> > USRP-users@lists.ettus.com
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> >
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
--
--
Sumit kumar
Doctoral Student, UPMC
Eurecom, BIOT
France
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Message: 7
Date: Mon, 11 Jul 2016 10:29:00 +0200
From: Sumit Kumar <cog...@gmail.com>
To: "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com>
Subject: [USRP-users] Format of complex data saved thru uhd_rx_cfile.
Is it Q15 ?
Message-ID:
<CAOExtcRmHUtrcoCOTF2BbXjnYx1q4gsw1mb=m7gfugshgqe...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Does the uhd_rx_cfile save the I and Q complex data in Q15 format. I
recorded the Wifi data, converted to .mat file and I see that its a very
small floating point value.
--
--
Sumit kumar
Doctoral Student, UPMC
Eurecom, BIOT
France
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Message: 8
Date: Mon, 11 Jul 2016 10:30:31 +0200
From: Sumit Kumar <cog...@gmail.com>
To: Vipin Sharma <vipinsha...@photonpace.com>
Cc: "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] Xilinx ISE for B210
Message-ID:
<caoextcshbciy6qlgskocq5vubafvkf-mu1vymxwgp-udlfs...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Look at this post
https://forums.xilinx.com/t5/Installation-and-Licensing/License-for-ISE-for-larger-Spartan-6-FPGA-XC6SLX150/td-p/530619
On Sun, Jul 10, 2016 at 4:40 AM, Vipin Sharma via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi,
>
> I would like to modify the default FPGA image by customizing the default
> Verilog source code. I assume I will need Xilinx ISE to achieve this. Is
> this going to be free or a license purchase is required from Xilinx?
>
> Thanks,
> Vipin
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
--
--
Sumit kumar
Doctoral Student, UPMC
Eurecom, BIOT
France
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Message: 9
Date: Mon, 11 Jul 2016 11:20:13 +0200
From: Marcus M?ller <marcus.muel...@ettus.com>
To: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] How to add interrupts on E310's Linux system
Message-ID: <a067cdd1-1793-b8f1-8a62-99cfd63f5...@ettus.com>
Content-Type: text/plain; charset="windows-1252"
You should probably refer to
http://files.ettus.com/manual/page_usrp_e3x0.html#e3x0_image_building to
understand how Ettus builds the filesystem images containing the kernel.
Basically, you want to add device tree files in layers, which influences
the build process.
You might want to look into the meta-ettus directory after building a
stock image, and understand where the .dts files are and how they play
together with the kernel build defined in meta-xilinx. These are the
things that define what version of the kernel is built, and what patches
are applied.
So, yes, you should use yocto/openembedded. A bit of Linux kernel dev
experience will be necessary to realize what you're planning to do; I'm
afraid copy & pasting from a specific example won't do the trick here :/
You said you're porting an existing GNSS system to the E310; that's a
cool application! Are you sure you need 13 different interrupt lines,
really? This sounds like the state machine your system inherently
becomes would be very hard to manage. What exactly do you need
interrupts for? Please excuse my curious questions; I'm currently
working very much with the mindset of someone who considers signals a
stream of samples, and thus, I don't often see the need for hardware
interrupts. Also, UHD has the capability to add timestamps and a bit of
user payload to sample packets, which might be a better choice for a
system running on a non-RT general purpose OS.
Best regards,
Marcus
On 11.07.2016 05:36, Weidong Wang via USRP-users wrote:
> Hi Moritz,
>
> Thanks again for your replies.
>
> I am migrating an existed GNSS system into E310. So I need to add at
> least 13 interrupts into E310's RFNOC system.
>
> I did some searches from Internet, and I fond this blog:
> <http://svenand.blogdrive.com/archive/203.html#.V4MP0O1VK1E>http://svenand.blogdrive.com/archive/203.html#.V4MP0O1VK1E
>
> The author of this blog explained how to add uio into zynq linux
> system using the petalinux, linux kernel and the device tree
> definition file system.dts.
>
> I want to know if I can use the same procedures to add the interrupts?
> Should I use yocto instead of petalinux, or together? And what's the
> linux kernel's version of E310 and where I can find the device tree
> definition file of E310?
>
> Best regards,
>
>
>
>
>
> <http://etsmtl.ca>
> <http://lassena.etsmtl.ca>
> <http://twitter.com/lassenaets>
> <http://www.linkedin.com/company/laboratoire-de-recherche-lassena>
> <http://www.facebook.com/lassena.etsmtl.ca> *Weidong WANG* |
> ?tudiant ? la Ma?trise
> Laboratoire LASSENA
> ?cole de technologie sup?rieure | 1100, rue Notre-Dame Ouest |
> Montr?al (Qc) Canada | H3C 1K3
> Tel.: 514 396-8800, poste 7930 | Bureau : A-2568 | www.etsmtl.ca
>
> Email : weidong.w...@lassena.etsmtl.ca
> LASSENA : lassena.etsmtl.ca <http://lassena.etsmtl.ca>
> /---------------------------------------------------------------------------------
>
> L??TS est une constituante du r?seau de l?Universit? du Qu?bec /
>
> ----------------------------------------------------------------------------------------------------------------------------
>
> Avis: L'information contenue dans ce courriel est strictement
> confidentielle. Toute utilisation par une personne autre que le
> destinataire est ill?gale.
> Si vous recevez ce courriel par erreur, veuillez svp le d?truire et
> nous en aviser.
> ----------------------------------------------------------------------------------------------------------------------------
>
> Notice: The information contained in this message is strictly
> confidential. Any use thereof by any person other than the named
> recipient(s) is illegal.
> If you are not the intended recipient please advise sender and delete
> this message.
>
>
> On 16-07-06 01:56 PM, Moritz Fischer wrote:
>> Hi Weidong,
>>
>> On Tue, Jul 5, 2016 at 12:52 PM, Weidong Wang via USRP-users
>> <usrp-users@lists.ettus.com> wrote:
>>> Hi all,
>>>
>>> I want to create a simple CE using RFNOC to generate an interrupt and send
>>> it to the ARM cpu.
>>>
>>> 1. Could I add this interrupt signal directly to the signal "IRQ_F2P" in
>>> e310.v?
>>>
>>> In e310.v line 415, we have :
>>>
>>> // Misc interrupts, GPIO, clk
>>> .IRQ_F2P({12'h0, pmu_irq, button_release_irq, button_press_irq,
>>> stream_irq}),
>> You can either use one of the remaining IRQ lines or turn a GPIO into
>> an IRQ source.
>>
>>> 2. How could I add it in linux system? I fond some topics about it for the
>>> regular linux systems, but it seems not useful for the system on E310.
>> At what level do you want to deal with the IRQ? Kernel? Userland? UHD
>> or RFNoC for that
>> matter currently doesn't have low level primitives do deal with
>> interrupts, nothing prevents you
>> from using techniques like UIO or writing a kernel module to receive
>> interrupts, though.
>>
>> Moritz
>
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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------------------------------
Message: 10
Date: Mon, 11 Jul 2016 07:37:19 -0400
From: James Humphries <james.humphr...@ettus.com>
To: Sumit Kumar <cog...@gmail.com>
Cc: Vipin Sharma <vipinsha...@photonpace.com>,
"usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] Xilinx ISE for B210
Message-ID:
<caewgfhueskuvkwenrpt_xny4y1n4sjj5j-kbzy_cnozmooq...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi Vipin,
As Sumit pointed out, yes, you would need a Xilinx seat. Here is some info
on the build process:
http://files.ettus.com/manual/md_usrp3_build_instructions.html
You will need Xilinx 14.7 specifically for the USRP B210.
-Trip
On Mon, Jul 11, 2016 at 4:30 AM, Sumit Kumar via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Look at this post
>
> https://forums.xilinx.com/t5/Installation-and-Licensing/License-for-ISE-for-larger-Spartan-6-FPGA-XC6SLX150/td-p/530619
>
>
>
>
> On Sun, Jul 10, 2016 at 4:40 AM, Vipin Sharma via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hi,
>>
>> I would like to modify the default FPGA image by customizing the default
>> Verilog source code. I assume I will need Xilinx ISE to achieve this. Is
>> this going to be free or a license purchase is required from Xilinx?
>>
>> Thanks,
>> Vipin
>>
>>
>> _______________________________________________
>> USRP-users mailing list
>> USRP-users@lists.ettus.com
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>
>
>
> --
> --
> Sumit kumar
> Doctoral Student, UPMC
> Eurecom, BIOT
> France
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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------------------------------
Message: 11
Date: Mon, 11 Jul 2016 14:33:26 +0000
From: Weidong Wang <wwd_u...@hotmail.com>
To: Marcus M?ller <marcus.muel...@ettus.com>,
"usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com>
Cc: "Landry, Rene Jr." <renejr.lan...@etsmtl.ca>, J?r?me Lecl?re
<jerome.lecl...@lassena.etsmtl.ca>
Subject: Re: [USRP-users] How to add interrupts on E310's Linux system
Message-ID:
<bl2pr03mb466ca2bf1de52c822248630f0...@bl2pr03mb466.namprd03.prod.outlook.com>
Content-Type: text/plain; charset="windows-1252"
Hi Marcus,
Thanks for your explanations.
We use these interrupts because we need compute through 1 kHz interrupt
sub-routine/channel. And GPS has 12 channels. All of our traces and
computations are in reel-time so I think the interrupts are necessary for this
project.
regards,
Weidong WANG | ?tudiant ? la Ma?trise
Laboratoire LASSENA
?cole de technologie sup?rieure | 1100, rue Notre-Dame Ouest |
Montr?al (Qc) Canada | H3C 1K3
Tel.: 514 396-8800, poste 7930 | Bureau : A-2568 | <http://www.etsmtl.ca>
www.etsmtl.ca<http://www.etsmtl.ca>
Email : <mailto:weidong.w...@lassena.etsmtl.ca>
weidong.w...@lassena.etsmtl.ca<mailto:weidong.w...@lassena.etsmtl.ca>
LASSENA : lassena.etsmtl.ca<http://lassena.etsmtl.ca>
---------------------------------------------------------------------------------
L??TS est une constituante du r?seau de l?Universit? du Qu?bec
----------------------------------------------------------------------------------------------------------------------------
Avis: L'information contenue dans ce courriel est strictement confidentielle.
Toute utilisation par une personne autre que le destinataire est ill?gale.
Si vous recevez ce courriel par erreur, veuillez svp le d?truire et nous en
aviser.
----------------------------------------------------------------------------------------------------------------------------
Notice: The information contained in this message is strictly confidential. Any
use thereof by any person other than the named recipient(s) is illegal.
If you are not the intended recipient please advise sender and delete this
message.
On 16-07-11 05:20 AM, Marcus M?ller via USRP-users wrote:
You should probably refer to
http://files.ettus.com/manual/page_usrp_e3x0.html#e3x0_image_building to
understand how Ettus builds the filesystem images containing the kernel.
Basically, you want to add device tree files in layers, which influences the
build process.
You might want to look into the meta-ettus directory after building a stock
image, and understand where the .dts files are and how they play together with
the kernel build defined in meta-xilinx. These are the things that define what
version of the kernel is built, and what patches are applied.
So, yes, you should use yocto/openembedded. A bit of Linux kernel dev
experience will be necessary to realize what you're planning to do; I'm afraid
copy & pasting from a specific example won't do the trick here :/
You said you're porting an existing GNSS system to the E310; that's a cool
application! Are you sure you need 13 different interrupt lines, really? This
sounds like the state machine your system inherently becomes would be very hard
to manage. What exactly do you need interrupts for? Please excuse my curious
questions; I'm currently working very much with the mindset of someone who
considers signals a stream of samples, and thus, I don't often see the need for
hardware interrupts. Also, UHD has the capability to add timestamps and a bit
of user payload to sample packets, which might be a better choice for a system
running on a non-RT general purpose OS.
Best regards,
Marcus
On 11.07.2016 05:36, Weidong Wang via USRP-users wrote:
Hi Moritz,
Thanks again for your replies.
I am migrating an existed GNSS system into E310. So I need to add at least 13
interrupts into E310's RFNOC system.
I did some searches from Internet, and I fond this blog:
<http://svenand.blogdrive.com/archive/203.html#.V4MP0O1VK1E>
http://svenand.blogdrive.com/archive/203.html#.V4MP0O1VK1E
The author of this blog explained how to add uio into zynq linux system using
the petalinux, linux kernel and the device tree definition file system.dts.
I want to know if I can use the same procedures to add the interrupts? Should I
use yocto instead of petalinux, or together? And what's the linux kernel's
version of E310 and where I can find the device tree definition file of E310?
Best regards,
[cid:part7.00090505.03010507@hotmail.com]<http://etsmtl.ca>
[cid:part9.03000004.04040205@hotmail.com]<http://lassena.etsmtl.ca>
[cid:part11.01020509.01020702@hotmail.com]<http://twitter.com/lassenaets>
[cid:part13.02020008.07010104@hotmail.com]
<http://www.linkedin.com/company/laboratoire-de-recherche-lassena>
[cid:part15.02090102.03070807@hotmail.com]
<http://www.facebook.com/lassena.etsmtl.ca> Weidong WANG | ?tudiant ?
la Ma?trise
Laboratoire LASSENA
?cole de technologie sup?rieure | 1100, rue Notre-Dame Ouest |
Montr?al (Qc) Canada | H3C 1K3
Tel.: 514 396-8800, poste 7930 | Bureau : A-2568 | <http://www.etsmtl.ca>
www.etsmtl.ca<http://www.etsmtl.ca>
Email : <mailto:weidong.w...@lassena.etsmtl.ca>
weidong.w...@lassena.etsmtl.ca<mailto:weidong.w...@lassena.etsmtl.ca>
LASSENA : lassena.etsmtl.ca<http://lassena.etsmtl.ca>
---------------------------------------------------------------------------------
L??TS est une constituante du r?seau de l?Universit? du Qu?bec
----------------------------------------------------------------------------------------------------------------------------
Avis: L'information contenue dans ce courriel est strictement confidentielle.
Toute utilisation par une personne autre que le destinataire est ill?gale.
Si vous recevez ce courriel par erreur, veuillez svp le d?truire et nous en
aviser.
----------------------------------------------------------------------------------------------------------------------------
Notice: The information contained in this message is strictly confidential. Any
use thereof by any person other than the named recipient(s) is illegal.
If you are not the intended recipient please advise sender and delete this
message.
On 16-07-06 01:56 PM, Moritz Fischer wrote:
Hi Weidong,
On Tue, Jul 5, 2016 at 12:52 PM, Weidong Wang via USRP-users
<usrp-users@lists.ettus.com><mailto:usrp-users@lists.ettus.com> wrote:
Hi all,
I want to create a simple CE using RFNOC to generate an interrupt and send
it to the ARM cpu.
1. Could I add this interrupt signal directly to the signal "IRQ_F2P" in
e310.v?
In e310.v line 415, we have :
// Misc interrupts, GPIO, clk
.IRQ_F2P({12'h0, pmu_irq, button_release_irq, button_press_irq,
stream_irq}),
You can either use one of the remaining IRQ lines or turn a GPIO into
an IRQ source.
2. How could I add it in linux system? I fond some topics about it for the
regular linux systems, but it seems not useful for the system on E310.
At what level do you want to deal with the IRQ? Kernel? Userland? UHD
or RFNoC for that
matter currently doesn't have low level primitives do deal with
interrupts, nothing prevents you
from using techniques like UIO or writing a kernel module to receive
interrupts, though.
Moritz
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com>
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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------------------------------
Message: 12
Date: Mon, 11 Jul 2016 17:34:55 +0200
From: Marcus M?ller <marcus.muel...@ettus.com>
To: Weidong Wang <wwd_u...@hotmail.com>, "usrp-users@lists.ettus.com"
<usrp-users@lists.ettus.com>
Cc: "Landry, Rene Jr." <renejr.lan...@etsmtl.ca>, J?r?me Lecl?re
<jerome.lecl...@lassena.etsmtl.ca>
Subject: Re: [USRP-users] How to add interrupts on E310's Linux system
Message-ID: <5783bc9f.4030...@ettus.com>
Content-Type: text/plain; charset="windows-1252"
Hi Weidong,
at these extremely low rates (a combined maximum of 12 kS/s), I'm not
convinced you'd need an interrupt for each of your channels. Personally,
I'd try to stay with the UHD architecture, and just modify the sample
handling in the FPGA to stream buffers that begin with some information
on to which channel they belong.
If you really want to stay with a separate data handling routine, using
a single interrupt for all 12 channels does sound sufficient.
Best regards,
Marcus
On 07/11/2016 04:33 PM, Weidong Wang wrote:
> Hi Marcus,
>
> Thanks for your explanations.
>
> We use these interrupts because we need compute through 1 kHz
> interrupt sub-routine/channel. And GPS has 12 channels. All of our
> traces and computations are in reel-time so I think the interrupts are
> necessary for this project.
>
> regards,
>
> *Weidong WANG* | ?tudiant ? la Ma?trise
> Laboratoire LASSENA
> ?cole de technologie sup?rieure | 1100, rue Notre-Dame Ouest |
> Montr?al (Qc) Canada | H3C 1K3
> Tel.: 514 396-8800, poste 7930 | Bureau : A-2568 | www.etsmtl.ca
>
> Email : weidong.w...@lassena.etsmtl.ca
> LASSENA : lassena.etsmtl.ca <http://lassena.etsmtl.ca>
> /---------------------------------------------------------------------------------
>
> L??TS est une constituante du r?seau de l?Universit? du Qu?bec
> /----------------------------------------------------------------------------------------------------------------------------
>
> Avis: L'information contenue dans ce courriel est strictement
> confidentielle. Toute utilisation par une personne autre que le
> destinataire est ill?gale.
> Si vous recevez ce courriel par erreur, veuillez svp le d?truire et
> nous en aviser.
> ----------------------------------------------------------------------------------------------------------------------------
>
> Notice: The information contained in this message is strictly
> confidential. Any use thereof by any person other than the named
> recipient(s) is illegal.
> If you are not the intended recipient please advise sender and delete
> this message.
>
> On 16-07-11 05:20 AM, Marcus M?ller via USRP-users wrote:
>>
>> You should probably refer to
>> http://files.ettus.com/manual/page_usrp_e3x0.html#e3x0_image_building
>> to understand how Ettus builds the filesystem images containing the
>> kernel. Basically, you want to add device tree files in layers, which
>> influences the build process.
>>
>> You might want to look into the meta-ettus directory after building a
>> stock image, and understand where the .dts files are and how they
>> play together with the kernel build defined in meta-xilinx. These are
>> the things that define what version of the kernel is built, and what
>> patches are applied.
>>
>> So, yes, you should use yocto/openembedded. A bit of Linux kernel dev
>> experience will be necessary to realize what you're planning to do;
>> I'm afraid copy & pasting from a specific example won't do the trick
>> here :/
>>
>> You said you're porting an existing GNSS system to the E310; that's a
>> cool application! Are you sure you need 13 different interrupt lines,
>> really? This sounds like the state machine your system inherently
>> becomes would be very hard to manage. What exactly do you need
>> interrupts for? Please excuse my curious questions; I'm currently
>> working very much with the mindset of someone who considers signals a
>> stream of samples, and thus, I don't often see the need for hardware
>> interrupts. Also, UHD has the capability to add timestamps and a bit
>> of user payload to sample packets, which might be a better choice for
>> a system running on a non-RT general purpose OS.
>>
>> Best regards,
>>
>> Marcus
>>
>>
>> On 11.07.2016 05:36, Weidong Wang via USRP-users wrote:
>>> Hi Moritz,
>>>
>>> Thanks again for your replies.
>>>
>>> I am migrating an existed GNSS system into E310. So I need to add
>>> at least 13 interrupts into E310's RFNOC system.
>>>
>>> I did some searches from Internet, and I fond this blog:
>>> <http://svenand.blogdrive.com/archive/203.html#.V4MP0O1VK1E>http://svenand.blogdrive.com/archive/203.html#.V4MP0O1VK1E
>>>
>>> The author of this blog explained how to add uio into zynq linux
>>> system using the petalinux, linux kernel and the device tree
>>> definition file system.dts.
>>>
>>> I want to know if I can use the same procedures to add the
>>> interrupts? Should I use yocto instead of petalinux, or together?
>>> And what's the linux kernel's version of E310 and where I can find
>>> the device tree definition file of E310?
>>>
>>> Best regards,
>>>
>>>
>>>
>>>
>>>
>>> <http://etsmtl.ca>
>>> <http://lassena.etsmtl.ca>
>>> <http://twitter.com/lassenaets>
>>> <http://www.linkedin.com/company/laboratoire-de-recherche-lassena>
>>> <http://www.facebook.com/lassena.etsmtl.ca> *Weidong WANG* |
>>> ?tudiant ? la Ma?trise
>>> Laboratoire LASSENA
>>> ?cole de technologie sup?rieure | 1100, rue Notre-Dame Ouest |
>>> Montr?al (Qc) Canada | H3C 1K3
>>> Tel.: 514 396-8800, poste 7930 | Bureau : A-2568 | www.etsmtl.ca
>>>
>>> Email : weidong.w...@lassena.etsmtl.ca
>>> LASSENA : lassena.etsmtl.ca <http://lassena.etsmtl.ca>
>>> /---------------------------------------------------------------------------------
>>>
>>> L??TS est une constituante du r?seau de l?Universit? du Qu?bec /
>>>
>>> ----------------------------------------------------------------------------------------------------------------------------
>>>
>>> Avis: L'information contenue dans ce courriel est strictement
>>> confidentielle. Toute utilisation par une personne autre que le
>>> destinataire est ill?gale.
>>> Si vous recevez ce courriel par erreur, veuillez svp le d?truire et
>>> nous en aviser.
>>> ----------------------------------------------------------------------------------------------------------------------------
>>>
>>> Notice: The information contained in this message is strictly
>>> confidential. Any use thereof by any person other than the named
>>> recipient(s) is illegal.
>>> If you are not the intended recipient please advise sender and
>>> delete this message.
>>>
>>>
>>> On 16-07-06 01:56 PM, Moritz Fischer wrote:
>>>> Hi Weidong,
>>>>
>>>> On Tue, Jul 5, 2016 at 12:52 PM, Weidong Wang via USRP-users
>>>> <usrp-users@lists.ettus.com> wrote:
>>>>> Hi all,
>>>>>
>>>>> I want to create a simple CE using RFNOC to generate an interrupt and send
>>>>> it to the ARM cpu.
>>>>>
>>>>> 1. Could I add this interrupt signal directly to the signal "IRQ_F2P" in
>>>>> e310.v?
>>>>>
>>>>> In e310.v line 415, we have :
>>>>>
>>>>> // Misc interrupts, GPIO, clk
>>>>> .IRQ_F2P({12'h0, pmu_irq, button_release_irq, button_press_irq,
>>>>> stream_irq}),
>>>> You can either use one of the remaining IRQ lines or turn a GPIO into
>>>> an IRQ source.
>>>>
>>>>> 2. How could I add it in linux system? I fond some topics about it for the
>>>>> regular linux systems, but it seems not useful for the system on E310.
>>>> At what level do you want to deal with the IRQ? Kernel? Userland? UHD
>>>> or RFNoC for that
>>>> matter currently doesn't have low level primitives do deal with
>>>> interrupts, nothing prevents you
>>>> from using techniques like UIO or writing a kernel module to receive
>>>> interrupts, though.
>>>>
>>>> Moritz
>>>
>>>
>>>
>>> _______________________________________________
>>> USRP-users mailing list
>>> USRP-users@lists.ettus.com
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>
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------------------------------
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------------------------------
End of USRP-users Digest, Vol 71, Issue 9
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