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Today's Topics:

   1. Re: Example code for a pair of TwinRXs (Samuel Dudley)
   2. Two questions about GPIO in E310 (Crozzoli Maurizio)
   3. FPGA code (Lihua Ren)
   4. Protective Enclosure for USRP B200mini Series Extends
      Operating Temperature Range (Wan Liu)
   5. Re: FPGA code (mle...@ripnet.com)


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Message: 1
Date: Mon, 19 Sep 2016 12:53:10 +0930
From: Samuel Dudley <dudley.sam...@gmail.com>
To: "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] Example code for a pair of TwinRXs
Message-ID:
        <camoat9wkt0bb9rcxotzg0mhh_7wq0wskxjyszrmvsqe_6+0...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"

Hi,
To add to the above request, I'm in the same situation (single X310 with 2
x TwinRX) but would prefer a gnuradio flow-graph demonstrating the 4
channel phase coherent receive.
Thanks,
Sam

On Sun, Sep 18, 2016 at 4:47 AM, d.des via USRP-users <
usrp-users@lists.ettus.com> wrote:

> > Derek Kozel is your "man" on this, and he and most of the Ettus R&D
> team have been away this week at GRCon.
>
> > You should be able to use independent-LO+timed-commands to achieve
> phase synchronization, but better is shared-LO mode, which is somewhat
> complicated, and Derek can probably provide an example flow-graph when
> he gets back from GRCon.
>
> Shared-LO seems like the right answer, so specific instructions for
> setting that up would be good.  I use the uhd API without Gnuradio but
> could probably pull what I need from a flow graph if that's easiest.
>
>
> >What type of interferometer?    For astronomy, or something else?
>
> It's for angle of arrival logging of pulsed signals.
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
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Message: 2
Date: Mon, 19 Sep 2016 13:07:13 +0000
From: Crozzoli Maurizio <maurizio.crozz...@telecomitalia.it>
To: "USRP-users@lists.ettus.com" <USRP-users@lists.ettus.com>
Cc: Disco Daniele <daniele.di...@telecomitalia.it>
Subject: [USRP-users] Two questions about GPIO in E310
Message-ID:
        <127beeb719684944b324013569c898fb@TELMBXD10BA020.telecomitalia.local>
Content-Type: text/plain; charset="us-ascii"

Hi!

I have the following two questions about GPIO pins in E310.

1. By observing the state of the pins along the whole boot process, it looks 
like at a certain time all pins are set to 1 (high voltage level) then they go 
back to 0: is there any way to avoid that behavior so that all pins never go 
high unwantedly?

2. Is there any chance in the future that an "official" modified version of the 
external mechanical metal box can be provided so that GPIO pins (with their 
small connector) can be accessed directly without having to make an 
"unofficial" hole in it.

TIA!

BR,
Maurizio.

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Grazie.

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------------------------------

Message: 3
Date: Mon, 19 Sep 2016 17:24:04 +0800 (CST)
From: "Lihua Ren" <anything...@163.com>
To: usrp-users@lists.ettus.com
Subject: [USRP-users] FPGA code
Message-ID: <6add2368.eed1.15741c27058.coremail.anything...@163.com>
Content-Type: text/plain; charset="gbk"

Hi,

I will creat a usrp3_rfnoc Vivado project  for building the X310 FPGA using the 
source files provided in Git.I am able to build ,but there are  had erros,which 
have many top-level. using the command line or adding files  directly. I have 
tried these methods but have a problem.Can you tell me how to creat the 
project?  
Thanks
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Message: 4
Date: Mon, 19 Sep 2016 09:01:46 -0500
From: Wan Liu <wan....@ettus.com>
To: usrp-users@lists.ettus.com
Subject: [USRP-users] Protective Enclosure for USRP B200mini Series
        Extends Operating Temperature Range
Message-ID:
        <caf7w4b6wsg+9y-jmfx7rkmo74mvohxbyduogw8ddp-idwqq...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"

Ettus Research is proud to announce the release of a steel enclosure for
the USRP B200mini Series product family. The enclosure provides protection
and extends the operating temperature range of the device. For the
commercial-grade USRP B200mini device, temperature range increases from 0 ?
40 ?C to -20 ? 60 ?C. For the industrial-grade USRP B200mini-i and
B205mini-i devices, temperature range increases from 0 ? 45 ?C to -40 ? 75
?C. Please visit the product page in the link below, or contact
i...@ettus.com, for additional information.


USRP B200mini Enclosure:
https://www.ettus.com/product/details/USRP-B200mini-enclosure

USRP B200mini-i Enclosure:
https://www.ettus.com/product/details/USRP-B200mini-i-enclosure

USRP B205mini-i Enclosure:
https://www.ettus.com/product/details/USRP-B205mini-i-enclosure

-- 
Wan Liu
Product Manager, Software Defined Radio
Ettus Research
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Message: 5
Date: Mon, 19 Sep 2016 10:05:57 -0400
From: mle...@ripnet.com
To: Lihua Ren <anything...@163.com>
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] FPGA code
Message-ID: <d549b4d5c76c60822693d7bd456e2...@ripnet.com>
Content-Type: text/plain; charset="us-ascii"

Have you spent any time with this page here: 

http://files.ettus.com/manual/md_usrp3_build_instructions.html 

On 2016-09-19 05:24, Lihua Ren via USRP-users wrote:

> Hi,
> 
> I will creat a usrp3_rfnoc Vivado project  for building the X310 FPGA using 
> the source files provided in Git.I am able to build ,but there are  had 
> erros,which have many top-level. using the command line or adding files  
> directly. I have tried these methods but have a problem.Can you tell me how 
> to creat the project?  
> 
> Thanks
> 
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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