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Today's Topics:

   1. Rugged and Weatherproof Software Defined Radio for Outdoor
      Deployment (Wan Liu)
   2. Re: E310 FPGA build Failure (Long, Jeffrey P.)
   3. E310 FPGA build Failure (Long, Jeffrey P.)
   4. Running FPGA Simulations for B205 mini (Steven Nicholas Alfano)
   5. Re: Running FPGA Simulations for B205 mini (Jonathon Pendlum)
   6. Re: E310 FPGA build Failure (Jonathon Pendlum)
   7. where can i find the source code of the samples in UHD (zhan siyu)
   8. Re: where can i find the source code of the samples in UHD
      (Marcus M?ller)
   9. Re: how to start the tx rx at the same time (Ekko)
  10. Complex taps for RFNoC FIR (????)
  11. Enclosure for B205mini-i (Vladica Sark)
  12. Can NI USRP 2953R work under GNU Radio? (wan...@seu.edu.cn)
  13. Re: Can NI USRP 2953R work under GNU Radio? (Marcus M?ller)
  14. Re: where can i find the source code of the samples in UHD
      (Marcus M?ller)
  15. R:  Two questions about GPIO in E310 (Disco Daniele)
  16. Re: UBX-160 Performance < 500 MHz (Perelman, Nathan)
  17. Re: UBX-160 Performance < 500 MHz (Marcus D. Leech)


----------------------------------------------------------------------

Message: 1
Date: Wed, 12 Oct 2016 13:17:42 -0500
From: Wan Liu <wan....@ettus.com>
To: usrp-users@lists.ettus.com
Subject: [USRP-users] Rugged and Weatherproof Software Defined Radio
        for Outdoor Deployment
Message-ID:
        <CAF7W4B53aTDXR4vp-Mdsyn0=Y9hFhtNcoyzkx8FCA6=fhyu...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"

Ettus Research is proud to announce the USRP E313, a rugged and
weatherproof software defined radio (SDR) designed for outdoor deployment.
The USRP E313 contains an embedded USRP E310 and is enclosed in an
IP67-rated enclosure to deliver ingress protection against dust and water,
with extensive testing to ensure operation under demanding environmental
conditions. Conveniently, you can use Power over Ethernet with surge and
lightning protection with the USRP E313.

This stand-alone SDR features a 2x2 MIMO transceiver that delivers up to 56
MHz of bandwidth spanning frequencies from 70 MHz to 6 GHz to cover
multiple bands of interest. The baseband processor uses the Xilinx
Zynq-7020 System-on-Chip for FPGA-accelerated computations combined with
stand-alone operation powered by a dual-core ARM CPU. To reduce your
development effort, the default OS supports USRP Hardware Driver (UHD), RF
Network-on-Chip (RFNoC) software API, and a variety of third party tools
such as GNU Radio. You can rapidly prototype and reliably deploy designs
for embedded applications intended for the unpredictable outdoors.

For more information, visit the USRP E313 product page linked below or
contact i...@ettus.com. We look forward to working with you on exciting and
innovative SDR applications.

USRP E313 Product Page:
https://www.ettus.com/product/details/USRP-E313

Best regards,

Wan Liu
Product Manager, Software Defined Radio
Ettus Research
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Message: 2
Date: Wed, 12 Oct 2016 20:07:04 +0000
From: "Long, Jeffrey P." <jpl...@mitre.org>
To: "USRP-users@lists.ettus.com" <USRP-users@lists.ettus.com>
Subject: Re: [USRP-users] E310 FPGA build Failure
Message-ID:
        
<dm5pr09mb13724f6d2ed08468a5268aacd9...@dm5pr09mb1372.namprd09.prod.outlook.com>
        
Content-Type: text/plain; charset="us-ascii"


I am trying to build a FPGA image for an E312 using the rfnoc-devel branch.

I issued this command:

./make.py ddc duc -d e310 -t E310_RFNOC_sg3

And it appears that the design ran over on resources. I thought I was building 
a pretty basic image but perhaps I have something wrong here.
Can you give some guidance on the usage of make.py? I also attached the 
build.log incase that sheds some light.

Thanks
Jeff
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Message: 3
Date: Wed, 12 Oct 2016 19:29:28 +0000
From: "Long, Jeffrey P." <jpl...@mitre.org>
To: "USRP-users@lists.ettus.com" <USRP-users@lists.ettus.com>
Subject: [USRP-users] E310 FPGA build Failure
Message-ID:
        
<dm5pr09mb13724aa29f2c71fc7d2abfbbd9...@dm5pr09mb1372.namprd09.prod.outlook.com>
        
Content-Type: text/plain; charset="us-ascii"

I am trying to build a FPGA image for an E312 using the rfnoc-devel branch.

I issued this command:

./make.py ddc duc -d e310 -t E310_RFNOC_sg3

And it appears that the design ran over on resources. I thought I was building 
a pretty basic image but perhaps I have something wrong here.
Can you give some guidance on the usage of make.py? I also attached the 
build.log incase that sheds some light.

Thanks
Jeff
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Message: 4
Date: Wed, 12 Oct 2016 16:27:35 -0400
From: Steven Nicholas Alfano <sna2...@columbia.edu>
To: usrp-users@lists.ettus.com
Subject: [USRP-users] Running FPGA Simulations for B205 mini
Message-ID:
        <CAFsM9mFed92_stnj6GEJ=jzzfck5dpmcqbmt4s+kucqyvj8...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"

Greetings,

I am trying to run FPGA simulations for a B205mini. I believe I have the
most up-to-date repository, but when I follow the instructions listed here:
https://files.ettus.com/manual/md_usrp3_sim_running_testbenches.html I run
into a few problems. I am trying to simulate using Vivado XSim. I am using
Vivado 2016.2.

First off, there's no setupenv.sh for the b2xxmini platform.

Second, there appears to be no make files in the b2xxmini directories for
simulation. The command 'make xsim' has no target.

I've attempted to run this from other usrp3 platforms as a guideline. For
instance, the e300 directory has a setupenv.sh script, but again I am
unable to run simulations.

Thank you for any help,
Steven
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Message: 5
Date: Wed, 12 Oct 2016 16:26:36 -0500
From: Jonathon Pendlum <jonathon.pend...@ettus.com>
To: Steven Nicholas Alfano <sna2...@columbia.edu>
Cc: "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] Running FPGA Simulations for B205 mini
Message-ID:
        <CAGdo0uSCM3ti_u0oXtTn=vhiurneuiw0d9azrc-+k+a+4e5...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"

Hi Steven,

We have a few locations where our test benches are located. Individual
component test benches are located at usrp3/lib/sim and
usrp3_rfnoc/lib/sim. RFNoC block simulations are located at
usrp3_rfnoc/lib/rfnoc. Device specific test benches are located in the
device's directory, such as usrp3/top/e300/sim and usrp3_rfnoc/top/x300/sim.

The B200 test benches use Xilinx's ISIM simulator which is included in ISE
14.7, the same tool you use to build B200 FPGA images. These test benches
are minimal and do not simulate the whole device.



Jonathon

On Wed, Oct 12, 2016 at 3:27 PM, Steven Nicholas Alfano via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Greetings,
>
> I am trying to run FPGA simulations for a B205mini. I believe I have the
> most up-to-date repository, but when I follow the instructions listed here:
> https://files.ettus.com/manual/md_usrp3_sim_running_testbenches.html I
> run into a few problems. I am trying to simulate using Vivado XSim. I am
> using Vivado 2016.2.
>
> First off, there's no setupenv.sh for the b2xxmini platform.
>
> Second, there appears to be no make files in the b2xxmini directories for
> simulation. The command 'make xsim' has no target.
>
> I've attempted to run this from other usrp3 platforms as a guideline. For
> instance, the e300 directory has a setupenv.sh script, but again I am
> unable to run simulations.
>
> Thank you for any help,
> Steven
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 6
Date: Wed, 12 Oct 2016 16:28:40 -0500
From: Jonathon Pendlum <jonathon.pend...@ettus.com>
To: "Long, Jeffrey P." <jpl...@mitre.org>
Cc: "USRP-users@lists.ettus.com" <USRP-users@lists.ettus.com>
Subject: Re: [USRP-users] E310 FPGA build Failure
Message-ID:
        <CAGdo0uR7BVFtKSuG1iG5Uhg79Ufm9pwhORLckm+j+iW4YvBS=q...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"

Hi Jeff,

We are working on reducing utilization on the DDC / DUC. One option is to
reduce the NUM_CHAINs option on the DDC to 1 to save some space. Also
unless you specifically need timed CORDIC tunes, you do not need a DDC or
DUC on the E310. Instead you can set the master clock rate to the sampling
rate you want.



Jonathon

On Wed, Oct 12, 2016 at 2:29 PM, Long, Jeffrey P. via USRP-users <
usrp-users@lists.ettus.com> wrote:

> I am trying to build a FPGA image for an E312 using the rfnoc-devel
> branch.
>
>
>
> I issued this command:
>
>
>
> ./make.py ddc duc -d e310 -t E310_RFNOC_sg3
>
>
>
> And it appears that the design ran over on resources. I thought I was
> building a pretty basic image but perhaps I have something wrong here.
>
> Can you give some guidance on the usage of make.py? I also attached the
> build.log incase that sheds some light.
>
>
>
> Thanks
>
> Jeff
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 7
Date: Thu, 13 Oct 2016 07:25:07 +0800
From: zhan siyu <zhansyu...@gmail.com>
To: usrp-users@lists.ettus.com
Subject: [USRP-users] where can i find the source code of the samples
        in UHD
Message-ID:
        <CAGNex4hbhGtAPo85o7WMj=8hx6tusxpzm0gYq=xemtnn2-h...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"

Hi everyone,

Sorry to bother you. I'm new to usrp. Right now, I want to implement a
simple applcation that make two E310 devices communicated. I checked the
documents of E310. I found there are two examples similiar to my
requirments. But where can I find the source code ?

The examples I'm interested in are in the "/usr/lib/uhd/examples ".

Best.

Siyu
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Message: 8
Date: Thu, 13 Oct 2016 01:31:26 +0200
From: Marcus M?ller <marcus.muel...@ettus.com>
To: zhan siyu <zhansyu...@gmail.com>,   zhan siyu via USRP-users
        <usrp-users@lists.ettus.com>,   usrp-users@lists.ettus.com
Subject: Re: [USRP-users] where can i find the source code of the
        samples in UHD
Message-ID: <138b2808-2c0e-43bf-a63c-742a832ee...@ettus.com>
Content-Type: text/plain; charset="utf-8"

https://github.com/EttusResearch/uhd/tree/master/host/examples

Am 13. Oktober 2016 01:25:07 MESZ, schrieb zhan siyu via USRP-users 
<usrp-users@lists.ettus.com>:
>Hi everyone,
>
>Sorry to bother you. I'm new to usrp. Right now, I want to implement a
>simple applcation that make two E310 devices communicated. I checked
>the
>documents of E310. I found there are two examples similiar to my
>requirments. But where can I find the source code ?
>
>The examples I'm interested in are in the "/usr/lib/uhd/examples ".
>
>Best.
>
>Siyu
>
>
>------------------------------------------------------------------------
>
>_______________________________________________
>USRP-users mailing list
>USRP-users@lists.ettus.com
>http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

-- 
Sent from my Android device with K-9 Mail. Please excuse my brevity.
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Message: 9
Date: Thu, 13 Oct 2016 12:05:23 +0800
From: Ekko <chai18740449...@gmail.com>
To: "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] how to start the tx rx at the same time
Message-ID:
        <caggob6ajxgcabwafuth7efkoo7v+m1gxzg_cncgkzbuckpw...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"

Hello Marcus

thanks for your answer?and i follw your reply to correct my program.

and there are some question about the UHD C API with tx_metadat,hope to get
your guide.

the first question,the meaning of full_sec and frac_sec,actually i did not
understand these two arguments well,with the output of
uhd_rx_metadata_time_spec,i think the full_sec is the Integer part of time
and the frac_sec is the decimal part,just like 1.2345S means the
full_sec=1,frac_sec=0.2345,i did't know whether this is right

the second question,about the argument of function uhd_tx_metadata_make()
full_sec and frac_sec,if i get the device time is
full=1,frac_time=0.3888,so i want the data is sent 0.002S later,so i need
set the function just like:
uhd_tx_metadata_make(&ms,true,1.0,0.3888+0.002,false,false),is this right?

the thirdquestion,i want to send the data continuously,just like
while(!stop_single_called){
     EXECUTE_OR_GOTO(free_tx_streamer,
            uhd_tx_streamer_send(tx_streamer, buffs_ptr, samps_per_buff,
&md, seconds_in_future+0.1, &num_samps_sent)
        )
        if(verbose){
            fprintf(stderr, "Sent %zu samples\n", num_samps_sent);
        }
}

and everytime i want to send data later not Immediately,so i need to add
the red part like this :
while(!stop_single_called){
      uhd_usrp_get_time_now(usrp,0,&full_second_now,&frac_time_now);
        seconds_in_future = frac_time_now + 0.02;
        EXECUTE_OR_GOTO(free_tx_streamer,
        uhd_tx_metadata_make(&md, true, full_second_now+0.0,
seconds_in_future, false, false)
        )
     EXECUTE_OR_GOTO(free_tx_streamer,
            uhd_tx_streamer_send(tx_streamer, buffs_ptr, samps_per_buff,
&md, seconds_in_future+0.1, &num_samps_sent)
        )
        if(verbose){
            fprintf(stderr, "Sent %zu samples\n", num_samps_sent);
        }
}

and i also got some LL at the begin of the program ,and after some time the
LL disappered,the program send data normally,so i think if the answer of
second question is right,why this program did not work well at first and
then work well after some time.

thank you

--Ekko
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Message: 10
Date: Thu, 13 Oct 2016 05:45:27 +0000
From: ???? <r...@eng.gov.il>
To: "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com>
Subject: [USRP-users] Complex taps for RFNoC FIR
Message-ID: <036aa0ce13154467bb6733de432ec...@eng.gov.il>
Content-Type: text/plain; charset="windows-1255"

Dear all,


I'm trying to use the RFNoC FIR block as a matched filter on E310 (release 4 
sg1 image).

I've noticed that in the fir_block_ctrl (fir_block_ctrl.hpp), the method 
set_taps() gets a vector of integers as taps.

Is there a way to filter with complex taps using RFNoC blocks?


Thanks,

Roy
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Message: 11
Date: Thu, 13 Oct 2016 10:09:44 +0200
From: Vladica Sark <vladicas...@gmail.com>
To: "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com>
Subject: [USRP-users] Enclosure for B205mini-i
Message-ID: <6899d13e-0dfd-e9c4-b73f-452397793...@gmail.com>
Content-Type: text/plain; charset=utf-8; format=flowed

Hi there,

I want to buy an enclosure for my b205mini-i, but there are 3 different 
enclosures which look that would fit. What is the difference between the 
3 enclosures offered for the B200mini series? The dimensions of the 
boards should be the same, so physically all board would fit to all of 
the enclosures offered.

BR,
Vladica



------------------------------

Message: 12
Date: Thu, 13 Oct 2016 21:11:52 +0800
From: "wan...@seu.edu.cn" <wan...@seu.edu.cn>
To: usrp-users <usrp-users@lists.ettus.com>
Subject: [USRP-users] Can NI USRP 2953R work under GNU Radio?
Message-ID: <2016101321113201146...@seu.edu.cn>
Content-Type: text/plain; charset="us-ascii"

Dear all,

I have an   NI USRP 2953. Can it work under GNU Radio with UHD.
If it works, how can I download the imag file and burn it into 2953?
Can I refer to the application note of X310  to setup it?

Thank you.

Best regards,
Dongming



wan...@seu.edu.cn
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Message: 13
Date: Thu, 13 Oct 2016 06:17:38 -0700
From: Marcus M?ller <marcus.muel...@ettus.com>
To: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Can NI USRP 2953R work under GNU Radio?
Message-ID: <ab788fa3-524f-fa61-c9c8-116dbb8a0...@ettus.com>
Content-Type: text/plain; charset="windows-1252"

Hi Dongming,

yes!

https://kb.ettus.com/Running_UHD_and_GNU_Radio_on_NI-USRP_RIO

Best regards,

Marcus


On 10/13/2016 06:11 AM, wangdm--- via USRP-users wrote:
> Dear all,
>
> I have an   NI USRP 2953. Can it work under GNU Radio with UHD.
> If it works, how can I download the imag file and burn it into 2953?
> Can I refer to the application note of X310  to setup it?
>
> Thank you.
>
> Best regards,
> Dongming
>
> ------------------------------------------------------------------------
> wan...@seu.edu.cn
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

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Message: 14
Date: Thu, 13 Oct 2016 06:19:35 -0700
From: Marcus M?ller <marcus.muel...@ettus.com>
To: zhan siyu <zhansyu...@gmail.com>, usrp-users
        <usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] where can i find the source code of the
        samples in UHD
Message-ID: <e8923989-7c21-a0c3-027a-33c9d958c...@ettus.com>
Content-Type: text/plain; charset="utf-8"

Hi Siyu,

just follow the normal build mechanism of the whole UHD; only the
modified parts will need to be recompiled after you've built it for the
first time.

https://kb.ettus.com/Software_Development_on_the_E310_and_E312

Best regards,

Marcus


On 10/12/2016 04:44 PM, zhan siyu wrote:
> Thanks very much.
>
> And furthermore, how can I compile my code if I do some modifications
> on it ?
>
> siyu
>
> 2016-10-13 7:31 GMT+08:00 Marcus M?ller <marcus.muel...@ettus.com
> <mailto:marcus.muel...@ettus.com>>:
>
>     https://github.com/EttusResearch/uhd/tree/master/host/examples
>     <https://github.com/EttusResearch/uhd/tree/master/host/examples>
>
>     Am 13. Oktober 2016 01:25:07 MESZ, schrieb zhan siyu via
>     USRP-users <usrp-users@lists.ettus.com
>     <mailto:usrp-users@lists.ettus.com>>:
>
>         Hi everyone,
>
>         Sorry to bother you. I'm new to usrp. Right now, I want to
>         implement a simple applcation that make two E310 devices
>         communicated. I checked the documents of E310. I found there
>         are two examples similiar to my requirments. But where can I
>         find the source code ? 
>
>         The examples I'm interested in are in the
>         "/usr/lib/uhd/examples ".
>
>         Best.
>
>         Siyu
>
>         
> ------------------------------------------------------------------------
>
>         USRP-users mailing list
>         USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
>         http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>         <http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com>
>
>     -- Sent from my Android device with K-9 Mail. Please excuse my
>     brevity.
>
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Message: 15
Date: Thu, 13 Oct 2016 14:39:58 +0000
From: Disco Daniele <daniele.di...@telecomitalia.it>
To: Nicolas Cuervo <nicolas.cue...@ettus.com>, Crozzoli Maurizio
        <maurizio.crozz...@telecomitalia.it>
Cc: "USRP-users@lists.ettus.com" <USRP-users@lists.ettus.com>
Subject: [USRP-users] R:  Two questions about GPIO in E310
Message-ID:
        <0554e4e055aa4c7ea96005b4c637dc84@TELMBXD07BA020.telecomitalia.local>
Content-Type: text/plain; charset="utf-8"

Thanks for your kind answer.
We found a solution by mean of pull-down resistors connected to the wire coming 
from the GPIO.
In our application, a not define status of the GPIO, can cause instability an 
trouble to the   other hw connected with the E310.

In any case Thank you for your support.

_____________________________________________
[logo1]
Daniele Disco
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Da: Nicolas Cuervo [mailto:nicolas.cue...@ettus.com]
Inviato: marted? 11 ottobre 2016 20:43
A: Crozzoli Maurizio
Cc: USRP-users@lists.ettus.com; Disco Daniele
Oggetto: Re: [USRP-users] Two questions about GPIO in E310

Hello Maurizio,
Sorry for the late response. We manage to go over your email without giving a 
response earlier. Have you come to an answer to your inquiry by yourself? If 
not, let me give you some insights:

I have the following two questions about GPIO pins in E310.

1. By observing the state of the pins along the whole boot process, it looks 
like at a certain time all pins are set to 1 (high voltage level) then they go 
back to 0: is there any way to avoid that behavior so that all pins never go 
high unwantedly?
To which part of the initialization are you referring to? After some discussion 
with my colleagues, we came down to three parts of the initialization process: 
power up (before FPGA is loaded, and UHD has not been applied), FPGA load 
(still UHD is not applying any control over GPIO) and UHD init.
During power-up, the GPIO is set to an state of high-impedance. This means that 
there is no internal control over the specific value of the GPIO output and, if 
you are measuring the voltage during this stage, the value that you are 
measuring basically depends on the external connections that you have attached 
to the pin.
Then, after the FPGA is loaded, for the E-series devices, the FPGA has GPIO 
pins and set them as pull-down by default. So, actually, during this part of 
the process, you should be seeing them with low values at the output.
Then, the SW comes into play, and the value that UHD sets to the GPIO depends 
basically on what the software is doing at the moment. A more detailed 
explanation about the role of UHD at this stage can be found here: 
http://files.ettus.com/manual/page_gpio_api.html
2. Is there any chance in the future that an "official" modified version of the 
external mechanical metal box can be provided so that GPIO pins (with their 
small connector) can be accessed directly without having to make an 
"unofficial" hole in it.

Regarding this, we are sorry to say that we don't have specific plans for this 
at the moment.
Cheers,
-Nicolas

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Grazie.

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Message: 16
Date: Thu, 13 Oct 2016 15:07:01 +0000
From: "Perelman, Nathan" <nperel...@lgsinnovations.com>
To: Michael West <michael.w...@ettus.com>, Ben Hilburn via USRP-users
        <usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] UBX-160 Performance < 500 MHz
Message-ID: <56cae6d2f48249f69e3a4673b232f...@lgs-ex01.lgsdirect.com>
Content-Type: text/plain; charset="utf-8"

Looking at this in more detail, does this affect the N2xx series USRPs? I don?t 
see any code in UHD to set the daughterboard clock rate for usrp2/N2xx USRPs, 
but I am seeing a fairly high noise floor with the UBX-40 in an N210 at low 
frequencies.

 

From: USRP-users [mailto:usrp-users-boun...@lists.ettus.com] On Behalf Of 
Perelman, Nathan via USRP-users
Sent: Monday, September 26, 2016 11:21 AM
To: Michael West
Cc: Ben Hilburn via USRP-users
Subject: Re: [USRP-users] UBX-160 Performance < 500 MHz

 

Does the dboard_clock_rate argument only affect the UBX or will it mess up the 
SBX or WBX daughterboards if set? I?m trying to figure out if I can code my 
application so it doesn?t care about which daughterboard is in use or if I have 
to code specially for the UBX. What version of UHD was support for the argument 
added in?

 

From: Michael West [mailto:michael.w...@ettus.com] 
Sent: Friday, September 23, 2016 2:43 PM
To: Perelman, Nathan
Cc: Ben Hilburn via USRP-users
Subject: Re: [USRP-users] UBX-160 Performance < 500 MHz

 

Hi Nathan,

If you plan on using frequencies both above and below 1 GHz, use the 20 MHz 
dboard_clock_rate.  A lower clock rate will mean a little more phase noise, but 
it should be fine for most applications.

Regards,

Michael

 

On Fri, Sep 23, 2016 at 10:27 AM, Perelman, Nathan 
<nperel...@lgsinnovations.com> wrote:

Is there a way to switch the daughterboard clock rate after creating a usrp 
object or can it only be set once on creation? What are the implications of 
using a clock rate of 20 MHz instead of 50 MHz when tuning above 1 GHz?

 

From: Michael West [mailto:michael.w...@ettus.com] 
Sent: Thursday, September 22, 2016 12:40 PM
To: Perelman, Nathan
Cc: Ben Hilburn via USRP-users


Subject: Re: [USRP-users] UBX-160 Performance < 500 MHz

 

Hi Nathan,

Yes.  Both UBX-40 and UBX-160 are affected.

Regards,

Michael

 

On Thu, Sep 22, 2016 at 7:09 AM, Perelman, Nathan via USRP-users 
<usrp-users@lists.ettus.com> wrote:

Does this affect the UBX-40 as well?

 

From: USRP-users [mailto:usrp-users-boun...@lists.ettus.com] On Behalf Of 
Michael West via USRP-users
Sent: Tuesday, September 20, 2016 1:05 PM
To: Michael Wentz
Cc: USRP-users@lists.ettus.com
Subject: Re: [USRP-users] UBX-160 Performance < 500 MHz

 

Hi Michael,

I'm glad to hear that made a substantial improvement.

 

We need to update the documentation with the dboard_clock_rate parameter 
information and we will do that.  The MAX2871 synthesizer used on the UBX has 
proven to be a bit touchy and has required a lot of special settings to perform 
properly.  The default dboard_clock_rate on the X310 is 50 MHz, which is the 
ideal PFD frequency for the UBX.  For frequencies under 1 GHz, we have found it 
necessary to reduce the dboard_clock_rate to 20 MHz due to several limitations 
in the MAX2871.

 

We looked into setting the dboard_clock_rate automatically in UHD, but it is a 
non-trivial exercise because it is dependent on the user's intended use.  
Changing the dboard_clock_rate dynamically whenever the user application 
changes the frequency presents a host of other potential problems, not to 
mention what to do if there are 2 different types of daughterboards in the USRP.

 

Regards,

Michael

 

 

 

On Tue, Sep 20, 2016 at 4:55 AM, Michael Wentz <mchlw...@gmail.com> wrote:

Hi Michael,

 

Adding "dboard_clock_rate=20e6" made a significant difference - the spurs and 
odd shape in the noise floor are both gone, image attached. I did the same type 
of measurement and it was around 75 dB SFDR, almost a 20 dB improvement.

 

I had never heard of the dboard_clock_rate argument before. Are there any 
implications of setting that to 20 MHz and using the default master clock rate 
of 200 MHz? Also, is there a reason that UHD wouldn't know to use that number 
by default (based on the fact that I'm using a UBX < 1 GHz)?

 

Thanks,

Michael

 

On Mon, Sep 19, 2016 at 9:34 PM, Michael West <michael.w...@ettus.com> wrote:

Hi Michael,

We do recommend a lower dboard clock rate for frequencies below 1 GHz on the 
UBX (for better LO performance).  Can you try adding 'dboard_clock_rate=20e6' 
to your device arguments and see if there is any change?

It is odd that introducing a signal causes the noise floor to rise.  I will run 
this by the hardware engineer for the UBX and see if he has any ideas.

 

Regards,

Michael West

 

On Mon, Sep 19, 2016 at 5:19 PM, Michael Wentz via USRP-users 
<usrp-users@lists.ettus.com> wrote:

I'm using the latest commit on rfnoc-devel, built today. I can also try without 
RFNoC but figured it would be identical since the master branch was merged in 
10 days ago.

 

On Mon, Sep 19, 2016 at 8:15 PM, Marcus D. Leech <mle...@ripnet.com> wrote:

On 09/19/2016 06:30 PM, Michael Wentz wrote:

Hi Marcus, 

 

Thanks for the feedback. Yes, I've tried gain ranges 0 to 31.5 - I'm intending 
to use an external LNA so was searching for settings where these issues were 
minimized, but they were fairly consistent across the gain range. I've also 
tried a variety of input signal strengths, usually around 30-40 dB below IIP3. 

 

I'm aware of the two RF chains and there is a noticeable performance difference 
< 500 MHz in the data on files.ettus.com, but nothing that informed me about 
the spurious content and odd behavior of the noise floor when there's a signal 
applied.

 

Is the UBX design more optimized for higher frequencies? Wondering if I should 
have gone with the WBX-120 here.

 

-Michael

The UBX design is optimized for its entire frequency range.  

What version of UHD are you using?

 

On Mon, Sep 19, 2016 at 6:03 PM, Marcus D. Leech via USRP-users 
<usrp-users@lists.ettus.com> wrote:

On 09/19/2016 02:58 PM, Michael Wentz via USRP-users wrote:

Hi,

I am working with an X310 and UBX-160 with the latest version of UHD. I've 
started to characterize the performance a bit at frequencies I'm interested in 
(< 500 MHz), and while trying to determine full range I noticed strange 
behavior compared to the WBX and SBX. Attached are some screen shots from 
measurements I made at 400 MHz with full gain (31.5) on the WBX-40, SBX-120, 
and UBX-160. I'm just eye balling the SDFR and picking the most noticeable spur 
away from the carrier, nothing really precise.

WBX-40 : input power -15 dBm, SFDR around 76 dB
SBX-120: input power -34 dBm, SFDR around 82 dB
UBX-120: input power -32 dBm, SFDR around 56 dB

I also noticed on the UBX that there is a significant increase in the noise 
floor when an input signal is applied, even if that input is 20-30 dB below 
where the input would clip. I've verified with test equipment that the noise 
floor is not from my signal source. Additionally, I did some measurements at 
600 MHz and 1 GHz and saw much better performance, in line with the WBX/SBX.

Is any of this expected? Is there anything I can do to improve the performance?

Thanks,
Michael

Two quick comments.

The first is that the analog RF chain on UBX is *very* different from SBX/WBX 
(which are almost identical, BTW, except for mixers).

The second is a question.  Have you tried dropping the gain on the UBX?  Have 
you tried lowering the signal level?  The UBX has two
  different RF chains, with 500Mhz being the dividing line between the two.   
So I would expect there to be not-subtle differences in things
  like OIP3, p1dB, etc.




_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

 

 

 


_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

 

 

 


_______________________________________________
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USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

 

 

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------------------------------

Message: 17
Date: Thu, 13 Oct 2016 11:17:27 -0400
From: "Marcus D. Leech" <mle...@ripnet.com>
To: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] UBX-160 Performance < 500 MHz
Message-ID: <57ffa587.9070...@ripnet.com>
Content-Type: text/plain; charset="windows-1252"; Format="flowed"

On 10/13/2016 11:07 AM, Perelman, Nathan via USRP-users wrote:
>
> Looking at this in more detail, does this affect the N2xx series 
> USRPs? I don?t see any code in UHD to set the daughterboard clock rate 
> for usrp2/N2xx USRPs, but I am seeing a fairly high noise floor with 
> the UBX-40 in an N210 at low frequencies.
>
My recollection is that DB clock-rate simply isn't settable on the 
N2xx--it's fixed by the hardware.


> *From:*USRP-users [mailto:usrp-users-boun...@lists.ettus.com] *On 
> Behalf Of *Perelman, Nathan via USRP-users
> *Sent:* Monday, September 26, 2016 11:21 AM
> *To:* Michael West
> *Cc:* Ben Hilburn via USRP-users
> *Subject:* Re: [USRP-users] UBX-160 Performance < 500 MHz
>
> Does the dboard_clock_rate argument only affect the UBX or will it 
> mess up the SBX or WBX daughterboards if set? I?m trying to figure out 
> if I can code my application so it doesn?t care about which 
> daughterboard is in use or if I have to code specially for the UBX. 
> What version of UHD was support for the argument added in?
>
> *From:*Michael West [mailto:michael.w...@ettus.com]
> *Sent:* Friday, September 23, 2016 2:43 PM
> *To:* Perelman, Nathan
> *Cc:* Ben Hilburn via USRP-users
> *Subject:* Re: [USRP-users] UBX-160 Performance < 500 MHz
>
> Hi Nathan,
>
> If you plan on using frequencies both above and below 1 GHz, use the 
> 20 MHz dboard_clock_rate.  A lower clock rate will mean a little more 
> phase noise, but it should be fine for most applications.
>
> Regards,
>
> Michael
>
> On Fri, Sep 23, 2016 at 10:27 AM, Perelman, Nathan 
> <nperel...@lgsinnovations.com <mailto:nperel...@lgsinnovations.com>> 
> wrote:
>
> Is there a way to switch the daughterboard clock rate after creating a 
> usrp object or can it only be set once on creation? What are the 
> implications of using a clock rate of 20 MHz instead of 50 MHz when 
> tuning above 1 GHz?
>
> *From:*Michael West [mailto:michael.w...@ettus.com 
> <mailto:michael.w...@ettus.com>]
> *Sent:* Thursday, September 22, 2016 12:40 PM
> *To:* Perelman, Nathan
> *Cc:* Ben Hilburn via USRP-users
>
>
> *Subject:* Re: [USRP-users] UBX-160 Performance < 500 MHz
>
> Hi Nathan,
>
> Yes. Both UBX-40 and UBX-160 are affected.
>
> Regards,
>
> Michael
>
> On Thu, Sep 22, 2016 at 7:09 AM, Perelman, Nathan via USRP-users 
> <usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>> wrote:
>
> Does this affect the UBX-40 as well?
>
> *From:*USRP-users [mailto:usrp-users-boun...@lists.ettus.com 
> <mailto:usrp-users-boun...@lists.ettus.com>] *On Behalf Of *Michael 
> West via USRP-users
> *Sent:* Tuesday, September 20, 2016 1:05 PM
> *To:* Michael Wentz
> *Cc:* USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
> *Subject:* Re: [USRP-users] UBX-160 Performance < 500 MHz
>
> Hi Michael,
>
> I'm glad to hear that made a substantial improvement.
>
> We need to update the documentation with the dboard_clock_rate 
> parameter information and we will do that.  The MAX2871 synthesizer 
> used on the UBX has proven to be a bit touchy and has required a lot 
> of special settings to perform properly.  The default 
> dboard_clock_rate on the X310 is 50 MHz, which is the ideal PFD 
> frequency for the UBX.  For frequencies under 1 GHz, we have found it 
> necessary to reduce the dboard_clock_rate to 20 MHz due to several 
> limitations in the MAX2871.
>
> We looked into setting the dboard_clock_rate automatically in UHD, but 
> it is a non-trivial exercise because it is dependent on the user's 
> intended use. Changing the dboard_clock_rate dynamically whenever the 
> user application changes the frequency presents a host of other 
> potential problems, not to mention what to do if there are 2 different 
> types of daughterboards in the USRP.
>
> Regards,
>
> Michael
>
> On Tue, Sep 20, 2016 at 4:55 AM, Michael Wentz <mchlw...@gmail.com 
> <mailto:mchlw...@gmail.com>> wrote:
>
> Hi Michael,
>
> Adding "dboard_clock_rate=20e6" made a significant difference - the 
> spurs and odd shape in the noise floor are both gone, image attached. 
> I did the same type of measurement and it was around 75 dB SFDR, 
> almost a 20 dB improvement.
>
> I had never heard of the dboard_clock_rate argument before. Are there 
> any implications of setting that to 20 MHz and using the default 
> master clock rate of 200 MHz? Also, is there a reason that UHD 
> wouldn't know to use that number by default (based on the fact that 
> I'm using a UBX < 1 GHz)?
>
> Thanks,
>
> Michael
>
> On Mon, Sep 19, 2016 at 9:34 PM, Michael West <michael.w...@ettus.com 
> <mailto:michael.w...@ettus.com>> wrote:
>
> Hi Michael,
>
> We do recommend a lower dboard clock rate for frequencies below 1 GHz 
> on the UBX (for better LO performance).  Can you try adding 
> 'dboard_clock_rate=20e6' to your device arguments and see if there is 
> any change?
>
> It is odd that introducing a signal causes the noise floor to rise.  I 
> will run this by the hardware engineer for the UBX and see if he has 
> any ideas.
>
> Regards,
>
> Michael West
>
> On Mon, Sep 19, 2016 at 5:19 PM, Michael Wentz via USRP-users 
> <usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>> wrote:
>
> I'm using the latest commit on rfnoc-devel, built today. I can also 
> try without RFNoC but figured it would be identical since the master 
> branch was merged in 10 days ago.
>
> On Mon, Sep 19, 2016 at 8:15 PM, Marcus D. Leech <mle...@ripnet.com 
> <mailto:mle...@ripnet.com>> wrote:
>
> On 09/19/2016 06:30 PM, Michael Wentz wrote:
>
>     Hi Marcus,
>
>     Thanks for the feedback. Yes, I've tried gain ranges 0 to 31.5 -
>     I'm intending to use an external LNA so was searching for settings
>     where these issues were minimized, but they were fairly consistent
>     across the gain range. I've also tried a variety of input signal
>     strengths, usually around 30-40 dB below IIP3.
>
>     I'm aware of the two RF chains and there is a noticeable
>     performance difference < 500 MHz in the data on files.ettus.com
>     <http://files.ettus.com>, but nothing that informed me about the
>     spurious content and odd behavior of the noise floor when there's
>     a signal applied.
>
>     Is the UBX design more optimized for higher frequencies? Wondering
>     if I should have gone with the WBX-120 here.
>
>     -Michael
>
> The UBX design is optimized for its entire frequency range.
>
> What version of UHD are you using?
>
> On Mon, Sep 19, 2016 at 6:03 PM, Marcus D. Leech via USRP-users 
> <usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>> wrote:
>
> On 09/19/2016 02:58 PM, Michael Wentz via USRP-users wrote:
>
> Hi,
>
> I am working with an X310 and UBX-160 with the latest version of UHD. 
> I've started to characterize the performance a bit at frequencies I'm 
> interested in (< 500 MHz), and while trying to determine full range I 
> noticed strange behavior compared to the WBX and SBX. Attached are 
> some screen shots from measurements I made at 400 MHz with full gain 
> (31.5) on the WBX-40, SBX-120, and UBX-160. I'm just eye balling the 
> SDFR and picking the most noticeable spur away from the carrier, 
> nothing really precise.
>
> WBX-40 : input power -15 dBm, SFDR around 76 dB
> SBX-120: input power -34 dBm, SFDR around 82 dB
> UBX-120: input power -32 dBm, SFDR around 56 dB
>
> I also noticed on the UBX that there is a significant increase in the 
> noise floor when an input signal is applied, even if that input is 
> 20-30 dB below where the input would clip. I've verified with test 
> equipment that the noise floor is not from my signal source. 
> Additionally, I did some measurements at 600 MHz and 1 GHz and saw 
> much better performance, in line with the WBX/SBX.
>
> Is any of this expected? Is there anything I can do to improve the 
> performance?
>
> Thanks,
> Michael
>
> Two quick comments.
>
> The first is that the analog RF chain on UBX is *very* different from 
> SBX/WBX (which are almost identical, BTW, except for mixers).
>
> The second is a question. Have you tried dropping the gain on the 
> UBX?  Have you tried lowering the signal level?  The UBX has two
>   different RF chains, with 500Mhz being the dividing line between the 
> two.   So I would expect there to be not-subtle differences in things
>   like OIP3, p1dB, etc.
>
>
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
>
> _______________________________________________
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> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

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