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Today's Topics:
1. Re: [IMAGE][FPGA] LUT's problem (Jonathon Pendlum)
2. Re: fail to transmit a signal by USRP/2901 using
gnuradio-companion software (Marcus M?ller)
3. Re: Overflows when doing repeated captures with X300
(Perelman, Nathan)
4. Re: B210 user registers (Long, Jeffrey P.)
5. Usrp sample rate (emre g?ng?r)
6. Usrp chirp rate pulsewidth limit (emre g?ng?r)
7. Re: Usrp sample rate (Fernando)
----------------------------------------------------------------------
Message: 1
Date: Fri, 10 Mar 2017 11:44:48 -0600
From: Jonathon Pendlum <[email protected]>
To: Rub?n Vogel <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] [IMAGE][FPGA] LUT's problem
Message-ID:
<CAGdo0uQx=yvyjft-wkosjxtokryqnccyvbgskxxv9z2j3_y...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi Ruben,
Try running without the "--fill-with-fifos" argument. Also, axi_dma_fifo
should be manually instantiated (instead of via uhd_image_builder) since it
requires special I/O to a DRAM controller.
Jonathon
On Fri, Mar 10, 2017 at 9:07 AM, Rub?n Vogel via USRP-users <
[email protected]> wrote:
> Hello everyone,
>
> I am trying to create a fpga image for Ettus E310, using Xilinx Vivado
> 2015.4, with the following blocks:
> --windows
> --axi_dma_fifo
> --fft
>
> Using the follow command:
>
> sudo python uhd_image_builder.py fft window axi_dma_fifo -d E310 -t
> E310_RFNOC -g -c --fill-with-fifos
>
> But during block synthesis, I get this error:
>
> Time (s): cpu = 00:11:33 ; elapsed = 00:09:28 . Memory (MB): peak =
> 8470.406 ; gain = 0.000 ; free physical = 3094 ; free virtual = 44037
> ERROR: [Place 30-484] The packing of lutram instances into lutram capable
> slices could not be obeyed.
>
> Number of LUTRAMs: 17168
> Theoretically, assuming any two LUTRAMs can be packed into a slice,
> the number of LUTRAM capable slices required is 4292 out of 4350 in the
> device (utilization 98.6667%)
> Actual number of LUTRAM capable slices required is 4373 out of 4350 in
> the device (utilization 100.529%).
>
> As a result, 20 or more LUTRAMs failed to place.
> Names of the first 20 LUTRAMs:
> zynq_fifo_top0/s2h_arbiter/stream_circuit[5].sts_fifo/
> fifo_short/gen_srlc32e[3].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[5].sts_fifo/
> fifo_short/gen_srlc32e[4].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[5].sts_fifo/
> fifo_short/gen_srlc32e[5].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[5].sts_fifo/fifo_short/o_tdata_reg[0]
> type FDRE
> zynq_fifo_top0/s2h_arbiter/stream_circuit[6].crl_addr_
> fifo/fifo_short/gen_srlc32e[30].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[6].crl_addr_
> fifo/fifo_short/gen_srlc32e[5].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[6].crl_addr_
> fifo/fifo_short/gen_srlc32e[8].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[6].crl_addr_
> fifo/fifo_short/gen_srlc32e[9].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[6].crl_size_
> fifo/fifo_short/gen_srlc32e[12].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[6].crl_size_
> fifo/fifo_short/gen_srlc32e[15].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[6].crl_size_
> fifo/fifo_short/gen_srlc32e[22].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[6].crl_size_
> fifo/fifo_short/gen_srlc32e[2].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[6].crl_size_
> fifo/fifo_short/gen_srlc32e[3].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[6].crl_size_
> fifo/fifo_short/gen_srlc32e[4].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[6].crl_size_
> fifo/fifo_short/gen_srlc32e[8].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[7].crl_addr_
> fifo/fifo_short/gen_srlc32e[23].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[7].crl_addr_
> fifo/fifo_short/gen_srlc32e[24].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[7].crl_addr_
> fifo/fifo_short/gen_srlc32e[27].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[7].crl_addr_
> fifo/fifo_short/gen_srlc32e[28].srlc32e type SRLC32E
> zynq_fifo_top0/s2h_arbiter/stream_circuit[7].crl_addr_
> fifo/fifo_short/gen_srlc32e[30].srlc32e type SRLC32E
>
> None of mentioned LUTRAMs is from any Pblock.
>
> Resolution: Please analyze your design to determine if the number of
> lutrams can be reduced by combining multiple lutrams into Block RAMs for
> example.
> ERROR: [Place 30-99] Placer failed with error: 'Could not place all
> lutrams'
> Please review all ERROR, CRITICAL WARNING, and WARNING messages during
> placement to understand the cause for failure.
> Ending Placer Task | Checksum: 113c459bc
>
> Time (s): cpu = 00:11:33 ; elapsed = 00:09:28 . Memory (MB): peak =
> 8470.406 ; gain = 0.000 ; free physical = 3094 ; free virtual = 44037
> INFO: [Common 17-83] Releasing license: Implementation
> 40 Infos, 82 Warnings, 18 Critical Warnings and 3 Errors encountered.
> place_design failed
> ERROR: [Common 17-69] Command failed: Placer could not place all instances
>
> Reading this error, I conclude that there is not enough space in the fpga
> to load all the blocks. But when I download the images developed by Ettus
> using 'uhd-images-downloader' and run 'uhd-usrp-probe', I see that the
> rfnoc image has 6 rfnoc blocks. I do not understand how I can not create an
> image with 3 rfnoc blocks. I hope you can help me, regards.
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 2
Date: Fri, 10 Mar 2017 21:06:24 +0100
From: Marcus M?ller <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] fail to transmit a signal by USRP/2901 using
gnuradio-companion software
Message-ID: <[email protected]>
Content-Type: text/plain; charset="windows-1252"
Hi Ozair,
I don't know whether someone already helped you. In case that didn't happen:
http://files.ettus.com/manual/page_transport.html#transport_usb_udev
should solve your issue.
Best regards,
Marcus
On 03/09/2017 08:32 AM, Ozair Iqbal via USRP-users wrote:
> Hi everyone,
> I am using USRP/2901 for my own experiments. When i
> connect USRP/2901 with my laptop, the USRP/2901 is easily
> detectable. But when i try to transmit a signal by making a
> flow graph in gnuradio-companion then following error message
> occurs at the terminal. I have provided the serial no in USRP
> source block (in gnuradio companion)
> but error is still there.
>
> UHD Error:
> USB open failed: insufficient permissions.
> See the application notes for your device.
> Traceback (most recent call last):
> File "/home/uzair/top_block.py", line 102, in <module>
> main()
> File "/home/uzair/top_block.py", line 96, in main
> tb = top_block_cls()
> File "/home/uzair/top_block.py", line 67, in __init__
> channels=range(1),
> File
> "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/__init__.py",
> line 122, in constructor_interceptor
> return old_constructor(*args)
> File
> "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/uhd_swig.py",
> line 2671, in make
> return _uhd_swig.usrp_source_make(*args)
> RuntimeError: LookupError: KeyError: No devices found for ----->
> Empty Device Address
>
> Regards,
> Ozair Iqbal
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 3
Date: Fri, 10 Mar 2017 20:31:39 +0000
From: "Perelman, Nathan" <[email protected]>
To: Ben Hilburn via USRP-users <[email protected]>
Subject: Re: [USRP-users] Overflows when doing repeated captures with
X300
Message-ID: <[email protected]>
Content-Type: text/plain; charset="us-ascii"
Has anyone at Ettus been able to test this and see if the same issue exists for
them? Or some idea of what might be going wrong?
-Nathan
From: USRP-users [mailto:[email protected]] On Behalf Of
Perelman, Nathan via USRP-users
Sent: Wednesday, March 8, 2017 12:23 PM
To: Ben Hilburn via USRP-users <[email protected]>
Subject: [USRP-users] Overflows when doing repeated captures with X300
When using the same multiusrp object to do repeated captures with an X300, I'm
seeing the 2nd (and 3rd, 4th) captures fail with an overflow error (D printed
out). Is there an additional wait step or sensor to wait on for the X300? This
same code works fine for repeated captures with an N210 and B210. To
demonstrate this issue, I added a loop to rx_samples_to_file to have it do
multiple captures (starting at line 333):
for(int i = 0; i < 4; i++)
{
std::cout << "Capture " << i << std::endl;
//recv to file
if (type == "double") recv_to_file<std::complex<double>
>recv_to_file_args("fc64");
else if (type == "float") recv_to_file<std::complex<float>
>recv_to_file_args("fc32");
else if (type == "short") recv_to_file<std::complex<short>
>recv_to_file_args("sc16");
else throw std::runtime_error("Unknown type " + type);
}
The output is:
$ ./rx_samples_to_file --args type=x300 --rate 6250000 --duration 1 --freq
800000000 --null
linux; GNU C++ version 5.3.1 20160406 (Red Hat 5.3.1-6); Boost_106000;
UHD_003.010.001.001-0-unknown
Creating the usrp device with: type=x300...
-- X300 initialization sequence...
-- Determining maximum frame size... 8000 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- Detecting internal GPSDO.... Found an internal GPSDO: LC_XO, Firmware Rev
0.929a
-- [DMA FIFO] Running BIST for FIFO 0... pass (Throughput: 1183.9MB/s)
-- [DMA FIFO] Running BIST for FIFO 1... pass (Throughput: 1186.0MB/s)
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
Using Device: Single USRP:
Device: X-Series Device
Mboard 0: X300
RX Channel: 0
RX DSP: 0
RX Dboard: A
RX Subdev: UBX RX
RX Channel: 1
RX DSP: 0
RX Dboard: B
RX Subdev: UBX RX
TX Channel: 0
TX DSP: 0
TX Dboard: A
TX Subdev: UBX TX
TX Channel: 1
TX DSP: 0
TX Dboard: B
TX Subdev: UBX TX
Setting RX Rate: 6.250000 Msps...
Actual RX Rate: 6.250000 Msps...
Setting RX Freq: 800.000000 MHz...
Actual RX Freq: 800.000000 MHz...
Waiting for "lo_locked": ++++++++++ locked.
Press Ctrl + C to stop streaming...
Capture 0
Capture 1
DGot an overflow indication. Please consider the following:
Your write medium must sustain a rate of 25.000000MB/s.
Dropped samples will not be written to the file.
Please modify this example for your purposes.
This message will not appear again.
Capture 2
DGot an overflow indication. Please consider the following:
Your write medium must sustain a rate of 25.000000MB/s.
Dropped samples will not be written to the file.
Please modify this example for your purposes.
This message will not appear again.
Capture 3
DGot an overflow indication. Please consider the following:
Your write medium must sustain a rate of 25.000000MB/s.
Dropped samples will not be written to the file.
Please modify this example for your purposes.
This message will not appear again.
Done!
Any ideas on where I might be going wrong?
-Nathan
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Message: 4
Date: Sat, 11 Mar 2017 04:31:10 +0000
From: "Long, Jeffrey P." <[email protected]>
To: Ian Buckley <[email protected]>, "[email protected]"
<[email protected]>
Subject: Re: [USRP-users] B210 user registers
Message-ID:
<dm5pr09mb13728a866f55c8fc08db2068d9...@dm5pr09mb1372.namprd09.prod.outlook.com>
Content-Type: text/plain; charset="utf-8"
Ian-
Sorry to resituate an old thread but I am having the same issue and not having
any success. I am porting an older E110 design and I wanted to keep using the
user registers however while the FPGA design has the code in it and I enabled
it by setting the param as shown below the UHD API seems to not have support
for it. In an older thread it was mentioned that Ettus had an internal branch
that did have support for that and they would consider pushing that out. I am
guessing that never happened. I attempted to do what Petr did below and copy
over stuff from B100_impl and while I got a clean compile it seg faulted so
there is probably something still missing. Any thoughts here?
Thanks
Jeff Long
From: USRP-users [mailto:[email protected]] On Behalf Of Ian
Buckley via USRP-users
Sent: Wednesday, April 27, 2016 3:25 AM
To: Petr Pracha?; [email protected]
Subject: Re: [USRP-users] B210 user registers
Petr, just to double check: You did enable user settings in the FPGA build? You
would do this by changing " .USER_SETTINGS(0), -> .USER_SETTINGS(1)," in
b200_core.v for both radio instances.
-Ian
Marcus, thank you for your answer, but what the Ian wrote is true. I have my
custom logic in FPGA and I need access to the registers resp. set_data
registers with set_addr: 8'd253 and 8'd254, which are reserved for user_setting
in Verilog code. I don?t understand why isn't any method for write to this
registers in UHD for B2X0 while for any others USRP is it.
I tried to implement the similar method, which is implemented in B100_impl.cpp.
This is the part of code which i wrote to the B200_impl.cpp and then a tried to
call function set_user_register(addr,data,0) in from main().
_user = user_settings_core_200::make(_local_ctrl, TOREG(253));
_tree->create<user_settings_core_200::user_reg_t>(mb_path / "user/regs")
.subscribe(boost::bind(&user_settings_core_200::set_reg, _user, _1));
I have build it without any error or warning, but it had no effect on the
registers in FPGA when I run the program.
Does anyone know how can I fix this problem? Thank you
On Tue, Apr 26, 2016 at 11:36 PM, Petr Pracha?
<[email protected]<mailto:[email protected]>> wrote:
Marcus, thank you for your answer, but what the Ian wrote is true. I have my
custom logic in FPGA and I need access to the registers resp. set_data
registers with set_addr: 8'd253 and 8'd254, which are reserved for user_setting
in Verilog code. I don?t understand why isn't any method for write to this
registers in UHD for B2X0 while for any others USRP is it.
I tried to implement the similar method, which is implemented in B100_impl.cpp.
This is the part of code which i wrote to the B200_impl.cpp and then a tried to
call function set_user_register(addr,data,0) in from main().
_user = user_settings_core_200::make(_local_ctrl, TOREG(253));
_tree->create<user_settings_core_200::user_reg_t>(mb_path / "user/regs")
.subscribe(boost::bind(&user_settings_core_200::set_reg, _user, _1));
I have build it without any error or warning, but it had no effect on the
registers in FPGA when I run the program.
Does anyone know how can I fix this problem? Thank you
On Tue, Apr 26, 2016 at 11:27 AM, Ian Buckley
<[email protected]<mailto:[email protected]>> wrote:
Marcus since Petr is asking about user settings specifically I suspect he has
enabled and connected his custom logic to the user_settings module in
radio_b200.v. Can you confirm please Petr?. This currently lacks for B2x0, as
Petr pointed out, access via the usual UHD API.
-Ian
On Tue, Apr 26, 2016 at 1:07 AM, Marcus M?ller
<[email protected]<mailto:[email protected]>> wrote:
Dear Petr,
interfacing with the registers is usually done via radio_ctrl_core_3000 on the
third-gen devices like the B2xx.
Which actual instance of that you want to use depends on which part of the B210
FPGA your settings register is connected ? there's the _local_ctrl, and one
radio_perifs[0,1].ctrl for each DSP chain in b200_impl .
Best regards,
Marcus
On 26.04.2016 06:23, Petr Pracha? via USRP-users wrote:
Hi,
I have USRP B210, and I need to write into user setting register in FPGA. Is
any easy way to do this? For many other radios (B100, N2x0, E100) is
implemented function set_user_register(). Why isn't implemented
user_setting_core in B200_impl.cpp? . It is really important to me, because I
have spend too many time with changing Verilog code, but its unusable without
ctrl from host computer.
Thank you for answer.
Petr
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Message: 5
Date: Sat, 11 Mar 2017 10:11:09 +0300
From: emre g?ng?r <[email protected]>
To: Ettus Research Support <[email protected]>,
[email protected]
Subject: [USRP-users] Usrp sample rate
Message-ID:
<CAJd1ueuuztXUSVodzORATV_jA9dwxTO0M=tndtinm__mkrm...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi,
I'm using NI2901 and I want to generate chirp signal which has 60MHz sample
rate.
But regardless of the signal type and center frequency I cannot reach this
sample rate. For more than 10MHz sample rate I take UUUOU... overflow stack
warnings.
I'm not sure that this usrp can reach 61.44MHz sample rate.
Is there anyway to reach 60MHz sample rate without UUO.. warnings?
Best regards.
Emre
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Message: 6
Date: Sat, 11 Mar 2017 10:35:44 +0300
From: emre g?ng?r <[email protected]>
To: Ettus Research Support <[email protected]>,
[email protected]
Subject: [USRP-users] Usrp chirp rate pulsewidth limit
Message-ID:
<CAJd1uesa=bxdk73gttebe9twh9ndw-fafoz6kusrmz+qlou...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi,
I want to generate chirp signal which has 50MHz bandwidth. (I use NI2901 it
can reach maximum 56MHz bandwidth)
I also want to has good pulsewidth for example 10microsec. For chirp signal
(lfm pulse signal);
bandwidth = pulsewidth*chirp rate
Chirp rate means that how fast the frequency changes. (for example
5MHz/1microsec speed)
I want to ask that what is max limits for pulsewidth and chirp rate for
NI2901.
Best regards.
Emre
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Message: 7
Date: Sat, 11 Mar 2017 10:22:48 +0100
From: Fernando <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] Usrp sample rate
Message-ID: <[email protected]>
Content-Type: text/plain; charset="windows-1252"
It may be a sw problem. For instance, if you use a low pass filter with
30Mhz cut off frequency and transition width 1Hz, the order of the
filter will be so high, your PC will not be able to process it and you
will get the overflow
regards
El 11/03/17 a las 08:11, emre g?ng?r via USRP-users escribi?:
> Hi,
>
> I'm using NI2901 and I want to generate chirp signal which has 60MHz
> sample rate.
>
> But regardless of the signal type and center frequency I cannot reach
> this sample rate. For more than 10MHz sample rate I take UUUOU...
> overflow stack warnings.
>
> I'm not sure that this usrp can reach 61.44MHz sample rate.
> Is there anyway to reach 60MHz sample rate without UUO.. warnings?
>
> Best regards.
> Emre
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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