You can use VHDL in RFNoC blocks, but it can be a bit tricky to embed. We might have an example coming out in a few weeks, but not right now.
Cheers, Martin On 07/06/2017 11:44 AM, Jason Matusiak via USRP-users wrote: > I have some code from a previous coworker that I would like to take > advantage of. Currently it is VHDL and their top block (which I am > calling), has things like: > USE WORK.TYPES.ALL; > USE WORK.HARDWARE.ALL; > USE WORK.MATH.ALL; > USE WORK.UTIL.ALL; > USE WORK.FILTERS.ALL; > USE WORK.RESAMPLERS.ALL; > > I understand that VHDL doesn't have a concept of include files, so > somehow I need to create a "work" library that can be called, right? > How do I go about doing this for my RFNoC OOT module? Is there an > example of this somewhere, or is my best bet just rewriting all his work > as Verilog? > > I know that I can open the Vivado gui with a GUI=1, but I wasn't sure if > I could then build the library and keep it in my OOT module. > > _______________________________________________ > USRP-users mailing list > [email protected] > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com _______________________________________________ USRP-users mailing list [email protected] http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
