Hello everyone,
We are designing a pseudo-random data generator using an LFSR register with
the Fibonacci method in RFNoC, to be implemented into the E310, taken as
reference the "SIGGEN" block provided in the RFNoC library. The problem is
that we do not have any data output and in the console of the GRC the
following message is shown during the execution of the model: timeout on
chan 0
VERSIÓN UHD = UHD_4.0.0.HEAD-239-g89427e8c
VERSIÓN GRC = 3.7.9.3
This was the construction of our block step by step:
1.
The verilog generator code was generated separately and its correct
operation was verified.
2.
Then, a new project was created using the “rfnocmodtool” tool.
3.
The file noc_block_’name’.v was modified, in which the code previously
generated at point 1 was introduced, in addition to the user registers
required for block operation (seed, enable and size_payload).
localparam [7:0] REG_SEED = 128;
localparam [7:0] REG_ENABLE = 129;
localparam [7:0] REG_PAY_SIZE = 130;
wire [31:0] o_seed;
wire [15:0] o_pay_size;
wire o_enable;
setting_reg #(.my_addr(REG_SEED), .awidth(8), .width(32), .at_reset(1))
set_seed (.clk(ce_clk), .rst(ce_rst), .strobe(set_stb), .addr(set_addr),
.in(set_data), .out(o_seed), .changed());
setting_reg #(.my_addr(REG_ENABLE), .awidth(8), .width(1), .at_reset(0))
set_enable (.clk(ce_clk), .rst(ce_rst), .strobe(set_stb), .addr(set_addr),
.in(set_data), .out(o_enable), .changed());
setting_reg #(.my_addr(REG_PAY_SIZE), .awidth(8), .width(16), .at_reset(4))
set_size (.clk(ce_clk), .rst(ce_rst), .strobe(set_stb), .addr(set_addr),
.in(set_data), .out(o_pay_size), .changed());
cvita_hdr_encoder cvita_hdr_encoder (.pkt_type(2'd0), .eob(1'd0),
.has_time(1'd0), .seqnum(12'd0), .payload_length(o_pay_size),
.dst_sid(next_dst_sid), .src_sid(src_sid), .vita_time(64'd0),
.header(s_axis_data_tuser));
//---------------LFSR-----------------------------
**Source code of the LFSR generator**
//-------------FIN LFSR ----------------------------
assign s_axis_data_tdata = salida;
assign s_axis_data_tvalid = lfsr_tvalid & o_enable;
assign lfsr_oready = s_axis_data_tready && o_enable;
4) The noc_block_tb.sv file was modified by adding the necessary tests, and
the correct functioning of the block in the RFNoC architecture was verified.
5) The FPGA image was generated with the custom block "sudo
./uhd_image_builder.py siggen lfsr -I <path to verilog> / fpga-src / -d
e310 -t E310_RFNOC -g"
6) The '.xml' file was modified for both UHD and GRC.
-- UHD .XML --
<nocblock>
<name>lfsr</name>
<blockname>lfsr</blockname>
<ids><id revision="0">26AF096D9D51FBC0</id></ids>
<registers>
<setreg>
<name>REG_SEED</name>
<address>128</address>
</setreg>
<setreg>
<name>REG_ENABLE</name>
<address>129</address>
</setreg>
<setreg>
<name>REG_PAY_SIZE</name>
<address>130</address>
</setreg>
</registers>
<args>
<arg>
<name>semilla</name>
<type>int</type>
<value>1</value>
<action>SR_WRITE("REG_SEED", $semilla)</action>
</arg>
<arg>
<name>encendido</name>
<type>int</type>
<value>0</value>
<action>SR_WRITE("REG_ENABLE", $encendido)</action>
</arg>
<arg>
<name>size</name>
<type>int</type>
<value>4</value>
<action>SR_WRITE("REG_PAY_SIZE", $size)</action>
</arg>
</args>
<ports>
<sink>
<name>dump</name>
</sink>
<source>
<name>src</name>
<type>sc32</type>
</source>
</ports>
</nocblock>
-- GRC .XML --
<block>
<name>RFNoC: lfsr</name>
<key>TESIS_lfsr</key>
<category>TESIS</category>
<import>import TESIS</import>
<make>TESIS.lfsr(self.device3, uhd.stream_args( cpu_format="fc32",
otw_format="sc16", args="",),
uhd.stream_args(cpu_format="fc32", otw_format="sc16", args="",),
$block_index,$device_index)
self.$(id).set_arg("semilla", $semilla)
self.$(id).set_arg("encendido", $encendido)
self.$(id).set_arg("size", $size)
</make>
<callback>set_arg("semilla", $semilla)</callback>
<callback>set_arg("encendido", $encendido)</callback>
<callback>set_arg("size", $size)</callback>
<param>
<name>Semilla</name>
<key>semilla</key>
<value>1</value>
<type>int</type>
</param>
<param>
<name>Payload</name>
<key>size</key>
<value>4</value>
<type>int</type>
</param>
<param>
<name>Encendido</name>
<key>encendido</key>
<type>int</type>
<option>
<name>True</name>
<key>1</key>
</option>
<option>
<name>False</name>
<key>0</key>
</option>
</param>
<param>
<name>Device Select</name>
<key>device_index</key>
<value>-1</value>
<type>int</type>
<hide>#if int($device_index()) < 0 then 'part' else 'none'#</hide>
<tab>RFNoC Config</tab>
</param>
<param>
<name>LFSR Select</name>
<key>block_index</key>
<value>-1</value>
<type>int</type>
<hide>#if int($block_index()) < 0 then 'part' else 'none'#</hide>
<tab>RFNoC Config</tab>
</param>
<param>
<name>FPGA Module Name</name>
<key>fpga_module_name</key>
<value>noc_block_lfsr</value>
<type>string</type>
<hide>all</hide>
<tab>RFNoC Config</tab>
</param>
<source>
<name>out</name>
<type>complex</type>
<vlen>$lfsr_out</vlen>
<domain>rfnoc</domain>
</source>
</block>
7) The lfsr_block_ctrl_impl.cpp file was modified to add the
"issue_stream_cmd" function in order to start and stop data generation.
Code was extracted from the siggen block.
using namespace uhd::rfnoc;
class lfsr_block_ctrl_impl : public lfsr_block_ctrl{
public:
UHD_RFNOC_BLOCK_CONSTRUCTOR(lfsr_block_ctrl){}
void issue_stream_cmd(const uhd::stream_cmd_t &stream_cmd, const size_t){
UHD_RFNOC_BLOCK_TRACE() << "issue_stream_cmd() " << std::endl;
if (not stream_cmd.stream_now) {throw uhd::not_implemented_error("siggen_block
does not support timed commands.");}
switch (stream_cmd.stream_mode) {
case uhd::stream_cmd_t::STREAM_MODE_START_CONTINUOUS:
sr_write("ENABLE", true);
break;
case uhd::stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS:
sr_write("ENABLE", false);
break;
case uhd::stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_DONE:
case uhd::stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_MORE:
throw uhd::not_implemented_error("siggen_block does not support streaming
modes other than CONTINUOUS");
default: UHD_THROW_INVALID_CODE_PATH();
}
}
UHD_RFNOC_BLOCK_REGISTER(lfsr_block_ctrl,"lfsr");
8) After loading the FPGA image in the device, the command "uhd_usrp_probe"
gives:
RFNoC blocks on this device:
| | |
| | | * Radio_0
| | | * lfsr_0
| | | * SigGen_0
9) The following GRC designs were generated:
lfsr --> time_sink
and
lfsr --> file_sink
But no data is obtained either in the time_sink or in the
file_sink.
If you can help or give us some recommendations to fix this problem we
would really appreciate it.
Thank you in advance.
Rubén O. Vogel
--
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