Sat Sep 9 08:04:37 2017 options author window_size category Custom comment description _enabled True _coordinate (8, 8) _rotation 0 generate_options qt_gui hier_block_src_path .: id top_block max_nouts 0 qt_qss_theme realtime_scheduling run_command {python} -u {filename} run_options prompt run True thread_safe_setters title variable comment _enabled True _coordinate (16, 251) _rotation 0 id freq value 1.2e9 variable comment _enabled True _coordinate (16, 331) _rotation 0 id gain value 0 variable comment _enabled True _coordinate (16, 419) _rotation 0 id gain_tx value 0 variable comment _enabled True _coordinate (8, 160) _rotation 0 id samp_rate value 2000000 blocks_null_sink alias bus_conns [[0,],] comment affinity _enabled True _coordinate (624, 377) _rotation 0 id blocks_null_sink_0 type complex num_inputs 6 vlen 1 uhd_usrp_sink alias ant0 bw0 0 center_freq0 freq norm_gain0 False gain0 gain_tx ant10 bw10 0 center_freq10 0 norm_gain10 False gain10 0 ant11 bw11 0 center_freq11 0 norm_gain11 False gain11 0 ant12 bw12 0 center_freq12 0 norm_gain12 False gain12 0 ant13 bw13 0 center_freq13 0 norm_gain13 False gain13 0 ant14 bw14 0 center_freq14 0 norm_gain14 False gain14 0 ant15 bw15 0 center_freq15 0 norm_gain15 False gain15 0 ant16 bw16 0 center_freq16 0 norm_gain16 False gain16 0 ant17 bw17 0 center_freq17 0 norm_gain17 False gain17 0 ant18 bw18 0 center_freq18 0 norm_gain18 False gain18 0 ant19 bw19 0 center_freq19 0 norm_gain19 False gain19 0 ant1 bw1 0 center_freq1 0 norm_gain1 False gain1 0 ant20 bw20 0 center_freq20 0 norm_gain20 False gain20 0 ant21 bw21 0 center_freq21 0 norm_gain21 False gain21 0 ant22 bw22 0 center_freq22 0 norm_gain22 False gain22 0 ant23 bw23 0 center_freq23 0 norm_gain23 False gain23 0 ant24 bw24 0 center_freq24 0 norm_gain24 False gain24 0 ant25 bw25 0 center_freq25 0 norm_gain25 False gain25 0 ant26 bw26 0 center_freq26 0 norm_gain26 False gain26 0 ant27 bw27 0 center_freq27 0 norm_gain27 False gain27 0 ant28 bw28 0 center_freq28 0 norm_gain28 False gain28 0 ant29 bw29 0 center_freq29 0 norm_gain29 False gain29 0 ant2 bw2 0 center_freq2 0 norm_gain2 False gain2 0 ant30 bw30 0 center_freq30 0 norm_gain30 False gain30 0 ant31 bw31 0 center_freq31 0 norm_gain31 False gain31 0 ant3 bw3 0 center_freq3 0 norm_gain3 False gain3 0 ant4 bw4 0 center_freq4 0 norm_gain4 False gain4 0 ant5 bw5 0 center_freq5 0 norm_gain5 False gain5 0 ant6 bw6 0 center_freq6 0 norm_gain6 False gain6 0 ant7 bw7 0 center_freq7 0 norm_gain7 False gain7 0 ant8 bw8 0 center_freq8 0 norm_gain8 False gain8 0 ant9 bw9 0 center_freq9 0 norm_gain9 False gain9 0 clock_rate 0.0 comment affinity dev_addr "addr=192.168.70.2" dev_args "" _enabled True _coordinate (648, 131) _rotation 0 id uhd_usrp_sink_0 type fc32 clock_source0 external sd_spec0 B:0 time_source0 external clock_source1 sd_spec1 time_source1 clock_source2 sd_spec2 time_source2 clock_source3 sd_spec3 time_source3 clock_source4 sd_spec4 time_source4 clock_source5 sd_spec5 time_source5 clock_source6 sd_spec6 time_source6 clock_source7 sd_spec7 time_source7 nchan 1 num_mboards 1 samp_rate samp_rate hide_cmd_port False stream_args stream_chans [] sync sync len_tag_name otw uhd_usrp_source alias ant0 bw0 0 center_freq0 freq dc_offs_enb0 "" iq_imbal_enb0 "" norm_gain0 False gain0 gain ant10 bw10 0 center_freq10 0 dc_offs_enb10 "" iq_imbal_enb10 "" norm_gain10 False gain10 0 ant11 bw11 0 center_freq11 0 dc_offs_enb11 "" iq_imbal_enb11 "" norm_gain11 False gain11 0 ant12 bw12 0 center_freq12 0 dc_offs_enb12 "" iq_imbal_enb12 "" norm_gain12 False gain12 0 ant13 bw13 0 center_freq13 0 dc_offs_enb13 "" iq_imbal_enb13 "" norm_gain13 False gain13 0 ant14 bw14 0 center_freq14 0 dc_offs_enb14 "" iq_imbal_enb14 "" norm_gain14 False gain14 0 ant15 bw15 0 center_freq15 0 dc_offs_enb15 "" iq_imbal_enb15 "" norm_gain15 False gain15 0 ant16 bw16 0 center_freq16 0 dc_offs_enb16 "" iq_imbal_enb16 "" norm_gain16 False gain16 0 ant17 bw17 0 center_freq17 0 dc_offs_enb17 "" iq_imbal_enb17 "" norm_gain17 False gain17 0 ant18 bw18 0 center_freq18 0 dc_offs_enb18 "" iq_imbal_enb18 "" norm_gain18 False gain18 0 ant19 bw19 0 center_freq19 0 dc_offs_enb19 "" iq_imbal_enb19 "" norm_gain19 False gain19 0 ant1 bw1 0 center_freq1 freq dc_offs_enb1 "" iq_imbal_enb1 "" norm_gain1 False gain1 gain ant20 bw20 0 center_freq20 0 dc_offs_enb20 "" iq_imbal_enb20 "" norm_gain20 False gain20 0 ant21 bw21 0 center_freq21 0 dc_offs_enb21 "" iq_imbal_enb21 "" norm_gain21 False gain21 0 ant22 bw22 0 center_freq22 0 dc_offs_enb22 "" iq_imbal_enb22 "" norm_gain22 False gain22 0 ant23 bw23 0 center_freq23 0 dc_offs_enb23 "" iq_imbal_enb23 "" norm_gain23 False gain23 0 ant24 bw24 0 center_freq24 0 dc_offs_enb24 "" iq_imbal_enb24 "" norm_gain24 False gain24 0 ant25 bw25 0 center_freq25 0 dc_offs_enb25 "" iq_imbal_enb25 "" norm_gain25 False gain25 0 ant26 bw26 0 center_freq26 0 dc_offs_enb26 "" iq_imbal_enb26 "" norm_gain26 False gain26 0 ant27 bw27 0 center_freq27 0 dc_offs_enb27 "" iq_imbal_enb27 "" norm_gain27 False gain27 0 ant28 bw28 0 center_freq28 0 dc_offs_enb28 "" iq_imbal_enb28 "" norm_gain28 False gain28 0 ant29 bw29 0 center_freq29 0 dc_offs_enb29 "" iq_imbal_enb29 "" norm_gain29 False gain29 0 ant2 bw2 0 center_freq2 freq dc_offs_enb2 "" iq_imbal_enb2 "" norm_gain2 False gain2 gain ant30 bw30 0 center_freq30 0 dc_offs_enb30 "" iq_imbal_enb30 "" norm_gain30 False gain30 0 ant31 bw31 0 center_freq31 0 dc_offs_enb31 "" iq_imbal_enb31 "" norm_gain31 False gain31 0 ant3 bw3 0 center_freq3 freq dc_offs_enb3 "" iq_imbal_enb3 "" norm_gain3 False gain3 gain ant4 bw4 0 center_freq4 freq dc_offs_enb4 "" iq_imbal_enb4 "" norm_gain4 False gain4 gain ant5 bw5 0 center_freq5 freq dc_offs_enb5 "" iq_imbal_enb5 "" norm_gain5 False gain5 gain ant6 bw6 0 center_freq6 freq dc_offs_enb6 "" iq_imbal_enb6 "" norm_gain6 False gain6 gain ant7 bw7 0 center_freq7 0 dc_offs_enb7 "" iq_imbal_enb7 "" norm_gain7 False gain7 0 ant8 bw8 0 center_freq8 0 dc_offs_enb8 "" iq_imbal_enb8 "" norm_gain8 False gain8 0 ant9 bw9 0 center_freq9 0 dc_offs_enb9 "" iq_imbal_enb9 "" norm_gain9 False gain9 0 clock_rate 0.0 comment affinity dev_addr "addr0=192.168.40.2,addr1=192.168.50.2,addr2=192.168.60.2,addr3=192.168.70.2" dev_args "" _enabled True _coordinate (200, 179) _rotation 0 id uhd_usrp_source_0 maxoutbuf 8192 clock_source0 external sd_spec0 A:0 B:0 time_source0 external clock_source1 external sd_spec1 A:0 B:0 time_source1 external clock_source2 external sd_spec2 A:0 B:0 time_source2 external clock_source3 external sd_spec3 A:0 time_source3 external clock_source4 sd_spec4 time_source4 clock_source5 sd_spec5 time_source5 clock_source6 sd_spec6 time_source6 clock_source7 sd_spec7 time_source7 minoutbuf 8192 nchan 7 num_mboards 4 type fc32 samp_rate samp_rate hide_cmd_port False stream_args stream_chans [] sync sync otw uhd_usrp_source_0 uhd_usrp_sink_0 0 0 uhd_usrp_source_0 blocks_null_sink_0 1 0 uhd_usrp_source_0 blocks_null_sink_0 2 1 uhd_usrp_source_0 blocks_null_sink_0 3 2 uhd_usrp_source_0 blocks_null_sink_0 4 3 uhd_usrp_source_0 blocks_null_sink_0 5 4 uhd_usrp_source_0 blocks_null_sink_0 6 5