Hi folks, I want to modify and build FPGA images using the Vivado GUI, however I’m still having problems with this. Here the procedure I have followed.
I have first set up the environment using the command “make X310_RFNOC_HG GUI=1” and then run the synthesis/implementation; this worked fine and I could build a correct image and load it onto the USRP. Then I modified just the rfnoc_ce_auto_inst_x310.v file (modification attached) in Vivado project mode and tried to build a new image with fewer CEs, as referred in http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2016-September/021709.html. However even though the building process did not show any error, after loading it onto the USRP I got the following error message: [INFO] [UHDlinux; GNU C++ version 4.8.4; Boost_105400; UHD_4.0.0.rfnoc-devel-369-g1908672f] [INFO] [X300] X300 initialization sequence... [INFO] [X300] Determining maximum frame size... [INFO] [X300] Maximum frame size: 1472 bytes. [INFO] [X300] Setup basic communication... [INFO] [X300] Loading values from EEPROM... [INFO] [X300] Setup RF frontend clocking... [INFO] [X300] Radio 1x clock:200 [INFO] [X300] Detecting internal GPSDO.... [INFO] [GPS] Found an internal GPSDO: LC_XO, Firmware Rev 0.929a [ERROR] [UHD] Exception caught in safe-call. in virtual ctrl_iface_impl::~ctrl_iface_impl() at /home/ltorresf/source/uhd/host/lib/rfnoc/ctrl_iface.cpp:76 this->peek32(0); -> EnvironmentError: IOError: Block ctrl (CE_00_Port_30) no response packet - AssertionError: bool(buff) in uint64_t ctrl_iface_impl::wait_for_ack(bool) at /home/ltorresf/source/uhd/host/lib/rfnoc/ctrl_iface.cpp:197 Error: EnvironmentError: IOError: Block ctrl (CE_00_Port_30) no response packet - AssertionError: bool(buff) in uint64_t ctrl_iface_impl::wait_for_ack(bool) at /home/ltorresf/source/uhd/host/lib/rfnoc/ctrl_iface.cpp:197 Has anyone had a similar problem and know how to solve it? Best, Luis
fnoc_ce_auto_inst_x310.v
Description: fnoc_ce_auto_inst_x310.v
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