John, will this be open source? We are also looking at modifying the SIGGEN
to add functionality. From the name it seems you are transmitting on two
channels. We would need more, but the concept seems similar.
On Wed, Sep 27, 2017 at 18:10 John Medrano via USRP-users <
[email protected]> wrote:
> Hello,
>
> We have modified sig_gen module to create an OOT module and we are
> attempting to build image. But we receive an error while trying to build
> the test bench.
>
> sig_gen relies on modules cadd, cordic_rotater, and axi_clip_complex. As
> seen below, it is unable to find these modules while building test bench.
>
> These files all exist with FPGA_SOURCE and are part of the original
> sig_gen module.
>
> Please advise.
>
> INFO: [VRFC 10-311] analyzing module glbl
> INFO: [USF-XSim-3] XSim::Elaborate design
> INFO: [USF-XSim-61] Executing 'ELABORATE' step in
> '/home/joseavila/Documents/gnuradio_source/rfnoc-siggen2ch/rfnoc/testbenches/noc_block_twochannelsiggen_tb/xsim_proj/xsim_proj.sim/sim_1/behav'
> Vivado Simulator 2015.4
> Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
> Running: /opt/Xilinx/Vivado/2015.4/bin/unwrapped/lnx64.o/xelab -wto
> b9f75645c2494d95a76a86ec25333ddc --debug all --relax --mt 8 -d
> WORKING_DIR=/home/joseavila/Documents/gnuradio_source/rfnoc-siggen2ch/rfnoc/testbenches/noc_block_twochannelsiggen_tb
> -L work -L unisims_ver -L unimacro_ver -L secureip --snapshot
> noc_block_twochannelsiggen_tb_behav work.noc_block_twochannelsiggen_tb
> work.glbl -log elaborate.log -timescale 1ns/1ns
> Using 8 slave threads.
> Starting static elaboration
> ERROR: [VRFC 10-2063] Module <cordic_rotator> not found while processing
> module instance <cordic_inst>
> [/usr/src/gnuradio_source/fpga/usrp3/lib/rfnoc/sine_tone.v:63]
> ERROR: [VRFC 10-2063] Module <cadd> not found while processing module
> instance <complexadd_sines>
> [/home/joseavila/Documents/gnuradio_source/rfnoc-siggen2ch/rfnoc/fpga-src/noc_block_twochannelsiggen.v:255]
> ERROR: [VRFC 10-2063] Module <axi_clip_complex> not found while processing
> module instance <clip_sinesum>
> [/home/joseavila/Documents/gnuradio_source/rfnoc-siggen2ch/rfnoc/fpga-src/noc_block_twochannelsiggen.v:265]
> ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design
> unit(s) in library work failed.
> INFO: [USF-XSim-99] Step results log
> file:'/home/joseavila/Documents/gnuradio_source/rfnoc-siggen2ch/rfnoc/testbenches/noc_block_twochannelsiggen_tb/xsim_proj/xsim_proj.sim/sim_1/behav/elaborate.log'
> ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check
> the Tcl console output or
> '/home/joseavila/Documents/gnuradio_source/rfnoc-siggen2ch/rfnoc/testbenches/noc_block_twochannelsiggen_tb/xsim_proj/xsim_proj.sim/sim_1/behav/elaborate.log'
> file for more information.
> # if [string equal $vivado_mode "batch"] {
> # puts "BUILDER: Closing project"
> # close_project
> # } else {
> # puts "BUILDER: In GUI mode. Leaving project open."
> # }
> BUILDER: Closing project
> ****** Webtalk v2015.4 (64-bit)
> **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
> **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
> ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
>
> source
> /home/joseavila/Documents/gnuradio_source/rfnoc-siggen2ch/rfnoc/testbenches/noc_block_twochannelsiggen_tb/xsim_proj/xsim_proj.hw/webtalk/labtool_webtalk.tcl
> -notrace
> INFO: [Common 17-206] Exiting Webtalk at Wed Sep 27 15:09:04 2017...
> INFO: [Common 17-206] Exiting Vivado at Wed Sep 27 15:09:04 2017...
> Built target noc_block_twochannelsiggen_tb
>
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>
--
Maj Tom Bereknyei
Defense Digital Service
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(571) 225-1630
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