OK, thanks! On Thu, Oct 5, 2017 at 11:58 AM, Nicolas Cuervo <[email protected]> wrote: > Hello Felipe, > > Please keep the conversation on the mailing list, as other users could find > the discussion helpful for their applications as well. > > We are aware of these critical warnings. Although not desired, they should > not affect your application. > > -N > > On Thu, Oct 5, 2017 at 10:52 AM, Felipe Augusto Pereira de Figueiredo > <[email protected]> wrote: >> >> Hi Nicolas, >> >> I've just done as you said (I have not checked the box that says >> "Import all files to the new project") and it worked fine, however, >> after trying to synthesize again, in the end of the synthesis process >> a window pops up with the following critical messages (see picture >> attached): >> >> [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC >> file >> /home/zz4fap/backup/fpga_lbt/fpga_lbt/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc >> will not be read for any cell of this module. >> [Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file >> >> /home/zz4fap/backup/fpga_lbt/fpga_lbt/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc >> will not be read for any cell of this module. >> [Common 17-55] 'set_property' expects at least one object. >> >> [/home/zz4fap/backup/fpga_lbt/fpga_lbt/uhd/fpga-src/usrp3/top/x300/timing.xdc:293] >> Resolution: If [get_<value>] was used to populate the object, check to >> make sure this command returns at least one valid object. >> [Common 17-55] 'set_property' expects at least one object. >> >> [/home/zz4fap/backup/fpga_lbt/fpga_lbt/uhd/fpga-src/usrp3/top/x300/timing.xdc:294] >> Resolution: If [get_<value>] was used to populate the object, check to >> make sure this command returns at least one valid object. >> [Common 17-55] 'set_property' expects at least one object. >> >> [/home/zz4fap/backup/fpga_lbt/fpga_lbt/uhd/fpga-src/usrp3/top/x300/timing.xdc:295] >> Resolution: If [get_<value>] was used to populate the object, check to >> make sure this command returns at least one valid object. >> [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC >> file >> /home/zz4fap/backup/fpga_lbt/fpga_lbt/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc >> will not be read for any cell of this module. >> >> Are those critical warnings OK? >> >> Thanks and Kind Regards, >> >> Felipe Augusto >> >> On Thu, Oct 5, 2017 at 6:29 AM, Nicolas Cuervo <[email protected]> >> wrote: >> > Felipe, >> > >> > Hmmm, do you mind being more specific regarding the part where the synth >> > fails? Copy/pasting the output you are getting would also be optimal. >> > >> > Trying my luck here: when the Vivado GUI pops up and you are able to >> > save >> > the project, be sure that you do NOT check the box that says "Import all >> > files to the new project" in the "save project" dialog, as doing >> > otherwise >> > is known for causing synth issues. Also, it would be better if you do >> > not >> > modify the path where the project is being saved, but only the name. Not >> > importing the file will preserve paths, and as long as the project is in >> > the >> > build folder, it should synthesize just fine. >> > >> > Regards, >> > -N >> > >> > >> > On Wed, Oct 4, 2017 at 10:11 PM, Felipe Augusto Pereira de Figueiredo >> > <[email protected]> wrote: >> >> >> >> Dear Nicolas, >> >> >> >> Thanks for your prompt reply! I missed that part regarding the >> >> rfnoc-devel branch. I will try with the devel branch and get back to >> >> you in case I find some problem. >> >> >> >> Yes, I'm able to stop it, however, when I save and try to synthesize >> >> the project again vivado complains that some files/libs are missing >> >> and I have not changed anything, I'm just trying to generate the image >> >> so that I know everything works without any modification from my side. >> >> >> >> Thanks and Kind Regards, >> >> >> >> Felipe Augusto >> >> >> >> On Wed, Oct 4, 2017 at 7:15 PM, Nicolas Cuervo >> >> <[email protected]> >> >> wrote: >> >> > Felipe, >> >> > >> >> > the uhd_image_builder.py [1] is located in the usual location >> >> > described >> >> > in >> >> > that guide [2]: >> >> > >> >> > path_to_fpga_repo/usrp3/tools/scripts/ >> >> > >> >> > Be sure to be pointing to the rfnoc-devel branch. >> >> > >> >> > I don't understand what you mean with "when I run make GUI=1 X310_HG >> >> > I'm >> >> > not >> >> > able to stop the synthesis". You should be able to do so when the >> >> > Vivado's >> >> > GUI pops up. This part of the process is the same when using the >> >> > command >> >> > you >> >> > described or the uhd_image_builder. >> >> > >> >> > Regards, >> >> > - Nicolas >> >> > >> >> > [1] >> >> > >> >> > >> >> > https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/tools/scripts/uhd_image_builder.py >> >> > [2] >> >> > >> >> > >> >> > https://kb.ettus.com/Debugging_FPGA_images#Save_the_project_and_finish_Synthesis >> >> > >> >> > On Wed, Oct 4, 2017 at 6:58 PM, Felipe Augusto Pereira de Figueiredo >> >> > via >> >> > USRP-users <[email protected]> wrote: >> >> >> >> >> >> Dear All, >> >> >> >> >> >> One question, I'm trying to add a chipscope to my project but I'm >> >> >> not >> >> >> finding uhd_image_builder.py script and when I run make GUI=1 >> >> >> X310_HG >> >> >> I'm not able to stop the synthesis and after the FPGA image is >> >> >> generated I save the project but I'm not able to use the saved >> >> >> project >> >> >> for adding my chipscope. >> >> >> >> >> >> I think the information here: >> >> >> https://kb.ettus.com/Debugging_FPGA_images is outdated. >> >> >> >> >> >> Have you removed the uhd_image_builder.py script? If so, is there a >> >> >> replacement for that script? >> >> >> >> >> >> Any hint will be very helpful! Thanks! >> >> >> >> >> >> Thanks and Kind Regards, >> >> >> >> >> >> Felipe Augusto >> >> >> >> >> >> _______________________________________________ >> >> >> USRP-users mailing list >> >> >> [email protected] >> >> >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> > >> >> > >> > >> > > >
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