[USRP-users] RFNoC Block with 2 inputs and 1 output

[Andrew Thommesen via USRP-users]

Hi all,

I am trying to create a custom RFNoC block with 2 inputs and 1 output. I have 
attached my block code as well as the XML files for the UHD and GNU radio 
integration. The block behaves as expected when I run the testbench. However, 
when synthesised and used within the GNU radio flowgraph it does not seem to 
output anything. Further investigation using chipscope revealed that 
m_axis_data_tvalid is only ever 0 or 1. In simulation, the value can be 3 when 
data is received on both input channels. This suggests that on the hardware I 
am not receiving data from both streams, which would explain why I never get 
any output. This may suggest that the XML files are incorrect? Does anyone know 
what I could be doing wrong?

Thanks,

Andy

<?xml version="1.0"?>
<!--Default XML file-->
<nocblock>
  <name>combiner</name>
  <blockname>combiner</blockname>
  <ids>
    <id revision="0">CF4CE20A208DF91B</id>
  </ids>
  <!--Two inputs, one output. If this is used, better have all the info the C++ file.-->
  <ports>
    <sink>
      <name>in0</name>
      <type>sc16</type>
      <port>0</port>
    </sink>
    <sink>
      <name>in1</name>
      <type>sc16</type>
      <port>1</port>
    </sink>
    <source>
      <name>out0</name>
      <type>sc16</type>
    </source>
  </ports>
</nocblock>

noc_block_combiner.v
Description: noc_block_combiner.v

<?xml version="1.0"?>
<block>
  <name>RFNoC: combiner</name>
  <key>tutorial_combiner</key>
  <category>tutorial</category>
  <import>import tutorial</import>
  <make>tutorial.combiner(
          self.device3,
          uhd.stream_args( # TX Stream Args
                cpu_format="fc32",
                otw_format="sc16",
                channels = (0,1),
                args="gr_vlen={0},{1}".format(${grvlen}, "" if $grvlen == 1 else "spp={0}".format($grvlen)),
          ),
          uhd.stream_args( # RX Stream Args
                cpu_format="fc32",
                otw_format="sc16",
                args="gr_vlen={0},{1}".format(${grvlen}, "" if $grvlen == 1 else "spp={0}".format($grvlen)),
          ),
          $block_index,$device_index
  )</make>
  <!-- Make one 'param' node for every Parameter you want settable from the GUI.
       Sub-nodes:
       * name
       * key (makes the value accessible as $keyname, e.g. in the make node)
       * type -->

  <param>
    <name>Host Data Type</name>
    <key>type</key>
    <type>enum</type>
    <option>
      <name>Complex float32</name>
      <key>fc32</key>
      <opt>type:complex</opt>
    </option>
    <option>
      <name>Complex int16</name>
      <key>sc16</key>
      <opt>type:sc16</opt>
    </option>
    <option>
      <name>Byte</name>
      <key>u8</key>
      <opt>type:byte</opt>
    </option>
    <option>
      <name>VITA word32</name>
      <key>item32</key>
      <opt>type:s32</opt>
    </option>
  </param>
  <!--RFNoC basic block configuration -->
  <param>
    <name>Device Select</name>
    <key>device_index</key>
    <value>-1</value>
    <type>int</type>
    <hide>#if int($device_index()) &lt; 0 then 'part' else 'none'#</hide>
    <tab>RFNoC Config</tab>
  </param>

  <param>
    <name>combiner Select</name>
    <key>block_index</key>
    <value>-1</value>
    <type>int</type>
    <hide>#if int($block_index()) &lt; 0 then 'part' else 'none'#</hide>
    <tab>RFNoC Config</tab>
  </param>

  <param>
    <name>FPGA Module Name</name>
    <key>fpga_module_name</key>
    <value>noc_block_combiner</value>
    <type>string</type>
    <hide>all</hide>
    <tab>RFNoC Config</tab>
  </param>

  <param>
    <name>Force Vector Length</name>
    <key>grvlen</key>
    <value>1</value>
    <type>int</type>
  </param>

  <param>
    <name>Device Format</name>
    <key>otw</key>
    <type>enum</type>
    <option>
      <name>Complex int16</name>
      <key>sc16</key>
    </option>
    <option>
      <name>Complex int8</name>
      <key>sc8</key>
    </option>
    <option>
      <name>Byte</name>
      <key>u8</key>
    </option>
  </param>

  <!-- Make one 'sink' node per input. Sub-nodes:
       * name (an identifier for the GUI)
       * type
       * vlen
       * optional (set to 1 for optional inputs) -->
  <sink>
    <name>in0</name>
    <type>complex</type>
    <vlen>$grvlen</vlen>
    <domain>rfnoc</domain>
  </sink>
  <sink>
    <name>in1</name>
    <type>complex</type>
    <vlen>$grvlen</vlen>
    <domain>rfnoc</domain>
  </sink>
  <!-- Make one 'source' node per output. Sub-nodes:
       * name (an identifier for the GUI)
       * type
       * vlen
       * optional (set to 1 for optional inputs) -->
  <source>
    <name>out</name>
    <type>complex</type>
    <vlen>$grvlen</vlen>
    <domain>rfnoc</domain>
  </source>
</block>

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