I tried doing the changes in uhd, and gr-ettus. I also tried changing that register value to 0 for the fpga and making a new e300.bit file. Any recommendations on how to troubleshoot? Also as I referenced, I'm doing this on a new e312 usrp.
Thanks, Jack On Wed, Nov 29, 2017 at 10:36 PM, Nick Foster <bistrom...@gmail.com> wrote: > It should still apply. Is there something specific you're having trouble > with? > > On Wed, Nov 29, 2017, 10:06 PM Jack Ziegler via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Has anyone recently tried rfnoc loopback? >> I tried following these directions: https://corvid.io/ >> 2017/04/22/stupid-rfnoc-tricks-loopback/ >> they are dated from last April. Not sure if I missed a step or maybe >> there is something new in gr-ettus and uhd-devel? >> >> Thanks, >> >> Jack Ziegler >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >
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