Nicolas,
Do you think that the timing to go radio->host->delay->radio is going
to be deterministic? I feared that it would be really jittery.
Thanks!!
-Dave
On Fri, Dec 22, 2017 at 9:22 AM, Nicolas Cuervo <nicolas.cue...@ettus.com>
wrote:
> Hi Dave,
>
> there is a delay fifo
> <https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/rfnoc/delay_fifo.v>
> module that you could pack in a custom FPGA image, but I think that you
> want to avoid re-synth. However, this rate might be too high to go around
> an FPGA modification. If you can uphold 100MSPS in the host, then In UHD
> there is no already coded delay, but you could set it up producing a series
> of zeros before your signal at the host, just as the GNU Radio delay block
> is doing it (or use the GNU Radio delay block
> <https://github.com/gnuradio/gnuradio/blob/master/gr-blocks/lib/delay_impl.cc>
> )
>
> -N
>
> On Thu, Dec 21, 2017 at 1:50 PM, Dave NotTelling via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Are there any pre-made modules or baked in ability to UHD/RFNOC that will
>> allow me to delay an entire 100 MSPS feed by up to single digit
>> milliseconds and then re-transmit? I imagine it could be done with a
>> custom FPGA image, but I'm hoping for an easy win.
>>
>> Thanks!
>>
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>>
>>
>
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