Hi Nick,
Thank you for your fast response. I am receiving the following errors: Synthesis [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_awprot[2] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_awprot[1] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_awprot[0] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_arprot[2] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_arprot[1] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_arprot[0] Implementation Design Initialization [Designutils 20-1281] Could not find module 'mig_7series_0'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc will not be read for this module. [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_hb31/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'axi_hb47'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_hb47/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc will not be read for any cell of this module. [Vivado 12-1387] No valid object(s) found for set_clock_groups constraint with option '-group [get_clocks -include_generated_clocks clk0]'. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":28] [Common 17-161] Invalid option value '#' specified for 'objects'. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":53] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":61] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":63] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":61] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":63] Opt Design [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] Place Design [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] Please let me know what you think. Thank you, Adam ________________________________ From: Nick Foster <bistrom...@gmail.com> Sent: Tuesday, January 2, 2018 12:08:20 PM To: Adam Kurisko Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] RFNOC Block design without GNU Radio The use of Gnuradio will not affect the FPGA design at all. If you supply the errors you're seeing we might be able to help further. Nick On Tue, Jan 2, 2018 at 8:57 AM Adam Kurisko via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hello all, I am trying to design an RFNoC block using Vivado 2015.4, but I keep running into synthesis and implementation critical warnings. Can you explain to me step by step how to instantiate a working rfnoc block WITHOUT using gnuradio? It seems that most information I am finding online include the use of gnuradio. I believe I have my environment setup correctly and I am calling the noc_shell and axi_wrapper modules within my blocks. However, the errors I am receiving are not stemming from the user code I have written, instead the errors are coming from various design sources within the e310 fpga source code. Please help. Thank you -Adam _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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