How do I use Jonathon's tb framework? Could you please provide the link to the manual/instructions if possible?
Also, thank you so much for helping me with this. I am still relatively new to RFNoC. Thank you, Adam ________________________________ From: Nick Foster <[email protected]> Sent: Tuesday, January 2, 2018 6:35:54 PM To: Adam Kurisko Cc: [email protected] Subject: Re: [USRP-users] RFNOC Block design without GNU Radio On a side note, this is a good time to mention that learning to simulate RFNoC blocks with the excellent and comprehensive testbench framework Jonathon put together is the single most effective way to write better RFNoC blocks, faster. This kind of error would be caught almost instantly in simulation, instead of waiting N minutes for Vivado to synthesize and implement it. It is absolutely worth your time to start working with the testbench now, instead of deferring because your block almost works. Nick On Tue, Jan 2, 2018 at 3:30 PM Nick Foster <[email protected]<mailto:[email protected]>> wrote: You're assigning to o_tready and o_tdata instead of s_axis_data_tready and s_axis_data_tdata. Incidentally, you're also not setting the "len" input to anything in the top-level instantiation. Nick On Tue, Jan 2, 2018 at 3:22 PM Adam Kurisko <[email protected]<mailto:[email protected]>> wrote: Okay, I am now using ce_clk in place of clk for my user code, however now my implementation is failing with the following error: Implementation Opt Design [DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net e310_core0/inst_delay_fifo/noc_shell/out_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout[0] has multiple drivers: e310_core0/inst_delay_fifo/sample_fifo/fifo_bram/ram/dst[0]_i_1/O, e310_core0/inst_delay_fifo/noc_shell/out_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[0]/Q. (63 more like this) [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run. What might be causing this now? Thank you, Adam ________________________________ From: Nick Foster <[email protected]<mailto:[email protected]>> Sent: Tuesday, January 2, 2018 6:02:44 PM To: Adam Kurisko Cc: [email protected]<mailto:[email protected]> Subject: Re: [USRP-users] RFNOC Block design without GNU Radio ce_clk is there for you to use as your compute engine clock. If you don't have a very good reason to generate and use another clock, you should use that one. Nick On Tue, Jan 2, 2018 at 2:57 PM Adam Kurisko <[email protected]<mailto:[email protected]>> wrote: I actually found that too and reverted it back to the the original bus_clk/rst and ce_bus/clk such as below: noc_block_delay_fifo inst_delay_fifo ( .bus_clk(bus_clk), .bus_rst(bus_rst), .ce_clk(ce_clk), .ce_rst(ce_rst), .i_tdata(ce_o_tdata[0]), .i_tlast(ce_o_tlast[0]), .i_tvalid(ce_o_tvalid[0]), .i_tready(ce_o_tready[0]), .o_tdata(ce_i_tdata[0]), .o_tlast(ce_i_tlast[0]), .o_tvalid(ce_i_tvalid[0]), .o_tready(ce_i_tready[0]), .debug(ce_debug[0]) ); I am unsure of why I changed that in the first place, but I think it may have been originally to route the ce_clk/rst to clk/rst as in .clk(ce_clk), .reset(ce_rst). For my user code in the source file, should I just use ce_clk rather than generating a new clk? Thank you, Adam ________________________________ From: Nick Foster <[email protected]<mailto:[email protected]>> Sent: Tuesday, January 2, 2018 5:09:55 PM To: Adam Kurisko Cc: [email protected]<mailto:[email protected]> Subject: Re: [USRP-users] RFNOC Block design without GNU Radio Why have you commented out bus_clk/rst and ce_clk/rst in favor of using clk/reset? And where are clk/reset/clear being generated? What is being used as bus_clk/rst in your block's noc_shell? Nick On Tue, Jan 2, 2018 at 12:54 PM Adam Kurisko <[email protected]<mailto:[email protected]>> wrote: Nick, Haven't heard back from you yet and was just wondering if you were able to give it a look. I have a feeling that i may have not instantiated the block correctly in rfnoc_ce_auto_inst.v, so I am currently attempting to figure out what might be wrong. Any help or insight into this scenario would be much appreciated. Thank you, Adam ________________________________ From: Adam Kurisko Sent: Tuesday, January 2, 2018 2:39:16 PM To: Nick Foster Cc: [email protected]<mailto:[email protected]> Subject: Re: [USRP-users] RFNOC Block design without GNU Radio Okay, below I posted my rfnoc_ce_auto_inst.v, as well as, my source code for noc_block_delay_fifo.v. ------------------------- rfnoc_ce_auto_inst.v ------------------------------ ///////////////////////////////////////////////////////// // Auto-generated by gen_rfnoc_inst.py! Any changes // in this file will be overwritten the next time // this script is run. ///////////////////////////////////////////////////////// localparam NUM_CE = 6; wire [NUM_CE*64-1:0] ce_flat_o_tdata, ce_flat_i_tdata; wire [63:0] ce_o_tdata[0:NUM_CE-1], ce_i_tdata[0:NUM_CE-1]; wire [NUM_CE-1:0] ce_o_tlast, ce_o_tvalid, ce_o_tready, ce_i_tlast, ce_i_tvalid, ce_i_tready; wire [63:0] ce_debug[0:NUM_CE-1]; // Flattern CE tdata arrays genvar k; generate for (k = 0; k < NUM_CE; k = k + 1) begin assign ce_o_tdata[k] = ce_flat_o_tdata[k*64+63:k*64]; assign ce_flat_i_tdata[k*64+63:k*64] = ce_i_tdata[k]; end endgenerate wire ce_clk = radio_clk; wire ce_rst = radio_rst; noc_block_delay_fifo inst_delay_fifo ( //.bus_clk(bus_clk), .bus_rst(bus_rst), //.ce_clk(ce_clk), .ce_rst(ce_rst), .clk(clk), .reset(reset), .clear(clear), .i_tdata(ce_o_tdata[0]), .i_tlast(ce_o_tlast[0]), .i_tvalid(ce_o_tvalid[0]), .i_tready(ce_o_tready[0]), .o_tdata(ce_i_tdata[0]), .o_tlast(ce_i_tlast[0]), .o_tvalid(ce_i_tvalid[0]), .o_tready(ce_i_tready[0]), .debug(ce_debug[0]) ); noc_block_axi_fifo_loopback inst_axi_fifo_loopback ( .bus_clk(bus_clk), .bus_rst(bus_rst), .ce_clk(ce_clk), .ce_rst(ce_rst), .i_tdata(ce_o_tdata[1]), .i_tlast(ce_o_tlast[1]), .i_tvalid(ce_o_tvalid[1]), .i_tready(ce_o_tready[1]), .o_tdata(ce_i_tdata[1]), .o_tlast(ce_i_tlast[1]), .o_tvalid(ce_i_tvalid[1]), .o_tready(ce_i_tready[1]), .debug(ce_debug[1]) ); noc_block_axi_fifo_loopback inst_axi_fifo_loopback2 ( .bus_clk(bus_clk), .bus_rst(bus_rst), .ce_clk(ce_clk), .ce_rst(ce_rst), .i_tdata(ce_o_tdata[2]), .i_tlast(ce_o_tlast[2]), .i_tvalid(ce_o_tvalid[2]), .i_tready(ce_o_tready[2]), .o_tdata(ce_i_tdata[2]), .o_tlast(ce_i_tlast[2]), .o_tvalid(ce_i_tvalid[2]), .o_tready(ce_i_tready[2]), .debug(ce_debug[2]) ); noc_block_axi_fifo_loopback inst_axi_fifo_loopback3 ( .bus_clk(bus_clk), .bus_rst(bus_rst), .ce_clk(ce_clk), .ce_rst(ce_rst), .i_tdata(ce_o_tdata[3]), .i_tlast(ce_o_tlast[3]), .i_tvalid(ce_o_tvalid[3]), .i_tready(ce_o_tready[3]), .o_tdata(ce_i_tdata[3]), .o_tlast(ce_i_tlast[3]), .o_tvalid(ce_i_tvalid[3]), .o_tready(ce_i_tready[3]), .debug(ce_debug[3]) ); noc_block_axi_fifo_loopback inst_axi_fifo_loopback4 ( .bus_clk(bus_clk), .bus_rst(bus_rst), .ce_clk(ce_clk), .ce_rst(ce_rst), .i_tdata(ce_o_tdata[4]), .i_tlast(ce_o_tlast[4]), .i_tvalid(ce_o_tvalid[4]), .i_tready(ce_o_tready[4]), .o_tdata(ce_i_tdata[4]), .o_tlast(ce_i_tlast[4]), .o_tvalid(ce_i_tvalid[4]), .o_tready(ce_i_tready[4]), .debug(ce_debug[4]) ); noc_block_axi_fifo_loopback inst_axi_fifo_loopback5 ( .bus_clk(bus_clk), .bus_rst(bus_rst), .ce_clk(ce_clk), .ce_rst(ce_rst), .i_tdata(ce_o_tdata[5]), .i_tlast(ce_o_tlast[5]), .i_tvalid(ce_o_tvalid[5]), .i_tready(ce_o_tready[5]), .o_tdata(ce_i_tdata[5]), .o_tlast(ce_i_tlast[5]), .o_tvalid(ce_i_tvalid[5]), .o_tready(ce_i_tready[5]), .debug(ce_debug[5]) ); --------------------------------------------------------------------------------------------- ------------------------- noc_block_delay_fifo.v ----------------------------------- module noc_block_delay_fifo #( parameter NOC_ID = 64'hDE7A_0000_0000_0000, parameter MAX_LEN_LOG2=10, parameter STR_SINK_FIFOSIZE = 11, parameter WIDTH=64) ( // input bus_clk, input bus_rst, // input ce_clk, input ce_rst, input clk, input reset, input clear, input [MAX_LEN_LOG2-1:0] len, input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready, output [WIDTH-1:0] debug ); //////////////////////////////////////////////////////////// // // RFNoC Shell // //////////////////////////////////////////////////////////// wire [31:0] set_data; wire [7:0] set_addr; wire set_stb; wire [63:0] cmdout_tdata, ackin_tdata; wire cmdout_tlast, cmdout_tvalid, cmdout_tready, ackin_tlast, ackin_tvalid, ackin_tready; wire [63:0] str_sink_tdata, str_src_tdata; wire str_sink_tlast, str_sink_tvalid, str_sink_tready, str_src_tlast, str_src_tvalid, str_src_tready; wire clear_tx_seqnum; wire [15:0] next_dst_sid; noc_shell #( .NOC_ID(NOC_ID), .STR_SINK_FIFOSIZE(STR_SINK_FIFOSIZE)) noc_shell ( .bus_clk(bus_clk), .bus_rst(bus_rst), .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready), .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), // Computer Engine Clock Domain .clk(ce_clk), .reset(ce_rst), // Control Sink .set_data(set_data), .set_addr(set_addr), .set_stb(set_stb), .set_time(), .rb_stb(1'b1), .rb_data(64'd0), .rb_addr(), // Control Source .cmdout_tdata(cmdout_tdata), .cmdout_tlast(cmdout_tlast), .cmdout_tvalid(cmdout_tvalid), .cmdout_tready(cmdout_tready), .ackin_tdata(ackin_tdata), .ackin_tlast(ackin_tlast), .ackin_tvalid(ackin_tvalid), .ackin_tready(ackin_tready), // Stream Sink .str_sink_tdata(str_sink_tdata), .str_sink_tlast(str_sink_tlast), .str_sink_tvalid(str_sink_tvalid), .str_sink_tready(str_sink_tready), // Stream Source .str_src_tdata(str_src_tdata), .str_src_tlast(str_src_tlast), .str_src_tvalid(str_src_tvalid), .str_src_tready(str_src_tready), // Stream IDs set by host .src_sid(), // SID of this block .next_dst_sid(next_dst_sid), // Next destination SID .resp_in_dst_sid(), // Response destination SID for input stream responses / errors .resp_out_dst_sid(), // Response destination SID for output stream responses / errors // Misc .vita_time(64'd0), .clear_tx_seqnum(clear_tx_seqnum), .debug(debug)); //////////////////////////////////////////////////////////// // // AXI Wrapper // Convert RFNoC Shell interface into AXI stream interface // //////////////////////////////////////////////////////////// wire [31:0] m_axis_data_tdata; wire m_axis_data_tlast; wire m_axis_data_tvalid; wire m_axis_data_tready; wire [31:0] s_axis_data_tdata; wire s_axis_data_tlast; wire s_axis_data_tvalid; wire s_axis_data_tready; localparam AXI_WRAPPER_BASE = 128; axi_wrapper #( .SIMPLE_MODE(1)) inst_axi_wrapper ( .clk(ce_clk), .reset(ce_rst), .clear_tx_seqnum(clear_tx_seqnum), .next_dst(next_dst_sid), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .i_tdata(str_sink_tdata), .i_tlast(str_sink_tlast), .i_tvalid(str_sink_tvalid), .i_tready(str_sink_tready), .o_tdata(str_src_tdata), .o_tlast(str_src_tlast), .o_tvalid(str_src_tvalid), .o_tready(str_src_tready), .m_axis_data_tdata(m_axis_data_tdata), .m_axis_data_tlast(m_axis_data_tlast), .m_axis_data_tvalid(m_axis_data_tvalid), .m_axis_data_tready(m_axis_data_tready), .s_axis_data_tdata(s_axis_data_tdata), .s_axis_data_tlast(s_axis_data_tlast), .s_axis_data_tvalid(s_axis_data_tvalid), .s_axis_data_tready(s_axis_data_tready), .m_axis_config_tdata(), .m_axis_config_tlast(), .m_axis_config_tvalid(), .m_axis_config_tready()); //////////////////////////////////////////////////////////// // // User code // //////////////////////////////////////////////////////////// reg [MAX_LEN_LOG2-1:0] full_count; wire full = full_count == len; wire do_op = i_tvalid & o_tready; assign i_tready = o_tready; assign o_tvalid = i_tvalid; wire [WIDTH-1:0] fifo_out; axi_fifo #(.WIDTH(WIDTH), .SIZE(MAX_LEN_LOG2)) sample_fifo (.clk(clk), .reset(reset), .clear(clear), .i_tdata(i_tdata), .i_tvalid(do_op), .i_tready(), .o_tdata(fifo_out), .o_tvalid(), .o_tready(do_op&full)); always @(posedge clk) if(reset | clear) full_count <= 0; else if(do_op & ~full) full_count <= full_count + 1; assign o_tdata = full ? fifo_out : 0; assign o_tlast = i_tlast; endmodule // noc_block_delay_fifo ------------------------------------------------------------------------------------- Thank you, Adam ________________________________ From: Nick Foster <[email protected]<mailto:[email protected]>> Sent: Tuesday, January 2, 2018 2:28:55 PM To: Adam Kurisko Cc: [email protected]<mailto:[email protected]> Subject: Re: [USRP-users] RFNOC Block design without GNU Radio Yeah, ok. It's that multiple driver that's the problem. Can you post the rfnoc_ce_auto_inst.v you're using? Nick On Tue, Jan 2, 2018, 10:58 AM Adam Kurisko <[email protected]<mailto:[email protected]>> wrote: Nick, I just attempted to generate a bitstream and it failed with the following errors. Most messages are the same as before, but take not of the errors present under "Opt Design" Vivado Commands General Messages [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_awprot[2] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_awprot[1] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_awprot[0] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_arprot[2] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_arprot[1] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_arprot[0] Synthesis [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_awprot[2] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_awprot[1] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_awprot[0] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_arprot[2] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_arprot[1] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_arprot[0] [Synth 8-3352] multi-driven net e310_core0/ce_o_tlast[0] with 1st driver pin 'e310_core0/inst_delay_fifo/noc_shell/out_fifo/fifo_short_2clk/dout[64]' ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/lib/fifo/axi_fifo_2clk.v":42] [Synth 8-3352] multi-driven net e310_core0/ce_o_tlast[0] with 2nd driver pin 'i_3847/O' ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/lib/control/axi_crossbar.v":19] Implementation Design Initialization [Designutils 20-1281] Could not find module 'mig_7series_0'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc will not be read for this module. [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_hb31/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'axi_hb47'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_hb47/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc will not be read for any cell of this module. [Vivado 12-1387] No valid object(s) found for set_clock_groups constraint with option '-group [get_clocks -include_generated_clocks clk0]'. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":28] [Common 17-161] Invalid option value '#' specified for 'objects'. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":53] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":61] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":63] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":61] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":63] Opt Design [DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net e310_core0/inst_delay_fifo/noc_shell/out_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout[64] has multiple drivers: e310_core0/axi_crossbar/instantiate_slave_mux[2].axi_slave_mux_i/fifo_short_2clk_i_1__5/O, e310_core0/inst_delay_fifo/noc_shell/out_fifo/fifo_short_2clk/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[64]/Q. [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run. design_1 General Messages [Designutils 20-1281] Could not find module 'mig_7series_0'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc will not be read for this module. [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_hb31/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'axi_hb47'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_hb47/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc will not be read for any cell of this module. [Vivado 12-1387] No valid object(s) found for set_clock_groups constraint with option '-group [get_clocks -include_generated_clocks clk0]'. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":28] [Common 17-161] Invalid option value '#' specified for 'objects'. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":53] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":61] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":63] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":61] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":63] Thank you, Adam ________________________________ From: Nick Foster <[email protected]<mailto:[email protected]>> Sent: Tuesday, January 2, 2018 12:35:54 PM To: Adam Kurisko Cc: [email protected]<mailto:[email protected]> Subject: Re: [USRP-users] RFNOC Block design without GNU Radio That all looks ok to me. Does it successfully generate a bitstream? There will virtually always be warnings, even some "critical" ones, in any sufficiently complex FPGA project. Nick On Tue, Jan 2, 2018, 9:26 AM Adam Kurisko <[email protected]<mailto:[email protected]>> wrote: Hi Nick, Thank you for your fast response. I am receiving the following errors: Synthesis [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_awprot[2] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_awprot[1] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_awprot[0] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_arprot[2] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_arprot[1] [Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin s_axi_arprot[0] Implementation Design Initialization [Designutils 20-1281] Could not find module 'mig_7series_0'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc will not be read for this module. [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_hb31/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'axi_hb47'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_hb47/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC file /home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc will not be read for any cell of this module. [Vivado 12-1387] No valid object(s) found for set_clock_groups constraint with option '-group [get_clocks -include_generated_clocks clk0]'. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":28] [Common 17-161] Invalid option value '#' specified for 'objects'. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":53] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":61] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":63] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":61] [Common 17-55] 'get_property' expects at least one object. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk/fifo_short_2clk_clocks.xdc":63] Opt Design [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] Place Design [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. ["/home/kurisko/e300/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc":58] Please let me know what you think. Thank you, Adam ________________________________ From: Nick Foster <[email protected]<mailto:[email protected]>> Sent: Tuesday, January 2, 2018 12:08:20 PM To: Adam Kurisko Cc: [email protected]<mailto:[email protected]> Subject: Re: [USRP-users] RFNOC Block design without GNU Radio The use of Gnuradio will not affect the FPGA design at all. If you supply the errors you're seeing we might be able to help further. Nick On Tue, Jan 2, 2018 at 8:57 AM Adam Kurisko via USRP-users <[email protected]<mailto:[email protected]>> wrote: Hello all, I am trying to design an RFNoC block using Vivado 2015.4, but I keep running into synthesis and implementation critical warnings. Can you explain to me step by step how to instantiate a working rfnoc block WITHOUT using gnuradio? It seems that most information I am finding online include the use of gnuradio. I believe I have my environment setup correctly and I am calling the noc_shell and axi_wrapper modules within my blocks. However, the errors I am receiving are not stemming from the user code I have written, instead the errors are coming from various design sources within the e310 fpga source code. Please help. Thank you -Adam _______________________________________________ USRP-users mailing list [email protected]<mailto:[email protected]> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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