Thanks for the explanations. I originally though the DDC block was only for the X310, but that makes more sense now, I figure I could retune while in a flowgraph by changing the ddc parameters.
10 Microseconds in fast enough for my current application (spectrum scanning for packets in different frequency channels), I'm also ignoring a fixed number of samples immediately after retuning to avoid having to check the updated sample rate from a gnuradio block that detects packets. Overflows are undesirable but are ok as long as they occur at intervals longer than the packets I'm capturing. On Thu, Jan 4, 2018 at 5:56 PM, EJ Kreinar <[email protected]> wrote: > Hi Jack, > > I'll hit the RFNoC side... > > > I have tried using the RFNOC USRP block, however, this block does not > have the "command" PMT message input for retuning while a flowgraph is > running. And a related question is that the RFNOC block only has a master > clock rate and a Bandwidth and no sample rate. Would it be safe to say the > when using this block with the E310, that the sample rate and the clock > rate are set to the same value always? > > This is correct. The "RFNoC Radio" GRC block attaches to the radio block > in the FPGA, and the output rate is equal to the master_clock_rate. > > If you set up the following RFNoC connections, you'll get comparable > functionality to the "USRP Source": > > RFNoC Radio -> RFNoC DDC -> Processor > > Using the RFNoC DDC, you can downsample from a master_clock_rate to your > desired sample rate (also, if you want an "LO offset", you'll need to > manually off-tune the RFNoC Radio center frequency, and then frequency > shift in the opposite direction in the RFNoC DDC). > > > > What I'm trying to do is rapidly retune between 24 Msps and 12 Msps, and > possibly other arbitrary rates too shortly > > How rapidly? Like, 10s of microseconds? Or several Hz? > > A fundamental limitation for both the B200 and the E310 when changing the > master_clock_rate or center frequency is going to be the characteristics of > the AD9361 chip itself... I'd refer to the datasheet/manual/source code > here, but there are definite switching penalties for changing center > frequency, and there are likely limitations on changing master_clock_rate, > too (you probably cant hit 10 microseconds when changing center frequency > or master_clock_rate). However, since the FPGA includes digital > downsampling performed in the DDC, you *should* be able to change the > sample rate between 24 and 12 Msps very easily... I'd imagine a "rapid" > sample rate change in the B200 relies on changing some digital downsampling > parameters. > > > I'd also be a little concerned trying to hit 12 Msps between the FPGA and > Processor on the E310. Usually my tests max out around 1 to 2 Msps > continuous streaming before I get Overflows. Have you had success with > these higher sample rates on the E310?? > > EJ > > On Thu, Jan 4, 2018 at 3:48 PM, Jack Ziegler via USRP-users < > [email protected]> wrote: > >> Hello, >> >> I'm using gnuradio with the usrp_source block. What I'm trying to do is >> rapidly retune between 24 Msps and 12 Msps, and possibly other arbitrary >> rates too shortly. >> >> This is easy to do with a B200 series radio using the usrp_source block >> and the command message port by sending a PMT message of the "rate" type. >> >> However, I'm now using an E310 and it will not easily retune. I can do >> 24 and 12 Msps by starting out with a 24 and 12 as the clock rate, however, >> the current API only allows setting the sample rate and not the clock rate >> during run time. Would it make sense for the E310 only to hack the >> usrp_source block code to set the clock rate and the sample rate at the >> same time? >> >> Also, I have a related question. I have tried using the RFNOC USRP block, >> however, this block does not have the "command" PMT message input for >> retuning while a flowgraph is running. And a related question is that the >> RFNOC block only has a master clock rate and a Bandwidth and no sample >> rate. Would it be safe to say the when using this block with the E310, >> that the sample rate and the clock rate are set to the same value always? >> >> Thanks >> >> Jack >> >> _______________________________________________ >> USRP-users mailing list >> [email protected] >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> >
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