Well Done! > I edited my custom block changing one of my wires from 'delay' to 'delay_val' > I have no idea if/why this would cause an issue, but my reasoning behind it might be that the compiler is getting confused when mapping the timing constraints. > Please let me know what you think about this?
Sounds like a red herring. Unless it fails timing and tells you, I wouldnt blame the timing constraints... that way lies madness. Neither would changing a wire name be a likely issue. I've personally had problems keeping track of my "rfnoc_ce_auto_inst" files-- it's easy to edit and then re-edit and lose an old copy, which might be the more likely culprit. If you'd like to convince yourself, perhaps try rebuilding again with the wire named "delay" instead of "delay_val". I'd be very surprised if it's a problem. Cheers, EJ On Wed, Jan 24, 2018 at 3:29 PM, Adam Kurisko <adamk...@outlook.com> wrote: > Hi EJ, > > > Good catch EJ. I actually caught that almost immediately after sending the > email and corrected it right away. > > > I do not think that was what was causing my initial errors, however I may > have just figured out the issue I was having. > > > I edited my custom block changing one of my wires from 'delay' to > 'delay_val' > > > I have no idea if/why this would cause an issue, but my reasoning behind > it might be that the compiler is getting confused when mapping the timing > constraints. > > > Please let me know what you think about this? > > > > Correcting the rfnoc_ce_auto_inst.v file may have also played a role in > this, however I am not sure why I would get that error initially with the > file being correct. > > > So, to fix it, I edited my noc block and corrected my rfnoc_ce_auto_inst.v > file. Then ran 'make clean' and 'make E310_RFNOC' > > > I am very glad I was successful. Thank you so much for your help. This was > my final output: > > > root@ettus-e3xx-sg1:~/localinstall/usr/share/uhd/images# uhd_usrp_probe > --args="fpga=usrp_e310_fpga_RFNOC.bit" > [INFO] [UHDlinux; GNU C++ version 4.9.2; Boost_105700; > UHD_4.0.0.rfnoc-devel-409-gec9138eb] > [INFO] [E300] Loading FPGA image: usrp_e310_fpga_RFNOC.bit... > [INFO] [E300] FPGA image loaded > [INFO] [E300] Initializing core control (global registers)... > > [INFO] [E300] Performing register loopback test... > [INFO] [E300] Register loopback test passed > [INFO] [RFNOC RADIO] Register loopback test passed > [INFO] [RFNOC RADIO] Register loopback test passed > [INFO] [AD936X] Performing CODEC loopback test... > [INFO] [AD936X] CODEC loopback test passed > [INFO] [AD936X] Performing CODEC loopback test... > [INFO] [AD936X] CODEC loopback test passed > [INFO] [CORES] Performing timer loopback test... > [INFO] [CORES] Timer loopback test passed > _____________________________________________________ > / > | Device: E-Series Device > | _____________________________________________________ > | / > | | Mboard: E3XX > | | product: 30674 > | | revision: 4 > | | serial: 308A556 > | | mac-addr: 00:80:2f:21:15:a2 > | | FPGA Version: 255.0 > | | FPGA git hash: bbd81be-dirty > | | RFNoC capable: Yes > | | > | | Time sources: none, internal, external > | | Clock sources: internal > | | Sensors: temp, ref_locked > | | _____________________________________________________ > | | / > | | | RX DSP: 0 > | | | > | | | Freq range: 0.000 to 0.000 MHz > | | _____________________________________________________ > | | / > | | | RX DSP: 1 > | | | > | | | Freq range: 0.000 to 0.000 MHz > | | _____________________________________________________ > | | / > | | | RX Dboard: A > | | | ID: E310 MIMO XCVR (0x0110) > | | | Serial: 308532C > | | | _____________________________________________________ > | | | / > | | | | RX Frontend: A > | | | | Name: FE-RX2 > | | | | Antennas: TX/RX, RX2 > | | | | Sensors: temp, rssi, lo_locked > | | | | Freq range: 50.000 to 6000.000 MHz > | | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB > | | | | Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | RX Frontend: B > | | | | Name: FE-RX1 > | | | | Antennas: TX/RX, RX2 > | | | | Sensors: temp, rssi, lo_locked > | | | | Freq range: 50.000 to 6000.000 MHz > | | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB > | | | | Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | RX Codec: A > | | | | Name: E3x0 RX dual ADC > | | | | Gain Elements: None > | | _____________________________________________________ > | | / > | | | TX DSP: 0 > | | | > | | | Freq range: 0.000 to 0.000 MHz > | | _____________________________________________________ > | | / > | | | TX DSP: 1 > | | | > | | | Freq range: 0.000 to 0.000 MHz > | | _____________________________________________________ > | | / > | | | TX Dboard: A > | | | ID: E310 MIMO XCVR (0x0110) > | | | Serial: 308532C > | | | _____________________________________________________ > | | | / > | | | | TX Frontend: A > | | | | Name: FE-TX2 > | | | | Antennas: TX/RX > | | | | Sensors: temp, lo_locked > | | | | Freq range: 50.000 to 6000.000 MHz > | | | | Gain range PGA: 0.0 to 89.8 step 0.2 dB > | | | | Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | TX Frontend: B > | | | | Name: FE-TX1 > | | | | Antennas: TX/RX > | | | | Sensors: temp, lo_locked > | | | | Freq range: 50.000 to 6000.000 MHz > | | | | Gain range PGA: 0.0 to 89.8 step 0.2 dB > | | | | Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | TX Codec: A > | | | | Name: E3x0 TX dual DAC > | | | | Gain Elements: None > | | _____________________________________________________ > | | / > | | | RFNoC blocks on this device: > | | | > | | | * Radio_0 > | | | * DELAY_0 > > It's so beautiful :') > > > Thank you, > > Adam Kurisko > ------------------------------ > *From:* EJ Kreinar <ejkrei...@gmail.com> > *Sent:* Wednesday, January 24, 2018 2:11:42 PM > *To:* Adam Kurisko > *Cc:* Martin Braun; USRP-users@lists.ettus.com > > *Subject:* Re: [USRP-users] [RFNoC] uhd_usrp_probe fails and throws > uhd::lookup_error > > Adam, > > In the rfnoc_ce_auto_inst.v you posted, it looks like the NUM_CE (6) does > not match your actual number of CEs (2): > > ``` > localparam NUM_CE = 6; // Must be no more than 14 (2 ports taken by > radio core & PS-PL DMA). > > wire [NUM_CE*64-1:0] ce_flat_o_tdata, ce_flat_i_tdata; > wire [63:0] ce_o_tdata[0:NUM_CE-1], ce_i_tdata[0:NUM_CE-1]; > wire [NUM_CE-1:0] ce_o_tlast, ce_o_tvalid, ce_o_tready, ce_i_tlast, > ce_i_tvalid, ce_i_tready; > wire [63:0] ce_debug[0:NUM_CE-1]; > > // Flattern CE tdata arrays > genvar k; > generate > for (k = 0; k < NUM_CE; k = k + 1) begin > assign ce_o_tdata[k] = ce_flat_o_tdata[k*64+63:k*64]; > assign ce_flat_i_tdata[k*64+63:k*64] = ce_i_tdata[k]; > end > endgenerate > > wire ce_clk = radio_clk; > wire ce_rst = radio_rst; > > noc_block_axi_fifo_loopback inst_noc_block_axi_fifo_loopback ( > .bus_clk(bus_clk), .bus_rst(bus_rst), > .ce_clk(ce_clk), .ce_rst(ce_rst), > .i_tdata(ce_o_tdata[0]), .i_tlast(ce_o_tlast[0]), > .i_tvalid(ce_o_tvalid[0]), .i_tready(ce_o_tready[0]), > .o_tdata(ce_i_tdata[0]), .o_tlast(ce_i_tlast[0]), > .o_tvalid(ce_i_tvalid[0]), .o_tready(ce_i_tready[0]), > .debug(ce_debug[0])); > > noc_block_delay_fifo inst_noc_block_delay_fifo ( > .bus_clk(bus_clk), .bus_rst(bus_rst), > .ce_clk(ce_clk), .ce_rst(ce_rst), > .i_tdata(ce_o_tdata[1]), .i_tlast(ce_o_tlast[1]), > .i_tvalid(ce_o_tvalid[1]), .i_tready(ce_o_tready[1]), > .o_tdata(ce_i_tdata[1]), .o_tlast(ce_i_tlast[1]), > .o_tvalid(ce_i_tvalid[1]), .o_tready(ce_i_tready[1]), > .debug(ce_debug[1])); > ``` > > I might recommend trying to use the uhd_image_builder.py or > uhd_image_builder_gui.py applications as described in the tutorial here: > https://kb.ettus.com/Getting_Started_with_RFNoC_Development > > EJ > > On Wed, Jan 24, 2018 at 12:09 PM, Adam Kurisko <adamk...@outlook.com> > wrote: > > Hi again EJ and Martin, > > > With the fresh install, I am still receiving the same error with a few > extra error lines now. The error is shown below. > > > root@ettus-e3xx-sg1:~/localinstall/usr/share/uhd/images# uhd_usrp_probe > --args="fpga=usrp_e310_fpga_RFNOC.bit"[INFO] [UHDlinux; GNU C++ version > 4.9.2; Boost_105700; UHD_4.0.0.rfnoc-devel-409-gec9138eb] > [INFO] [E300] Loading FPGA image: usrp_e310_fpga_RFNOC.bit... > [INFO] [E300] FPGA image loaded > [INFO] [E300] Initializing core control (global registers)... > > [INFO] [E300] Performing register loopback test... > [INFO] [E300] Register loopback test passed > [INFO] [RFNOC RADIO] Register loopback test passed > [INFO] [RFNOC RADIO] Register loopback test passed > [ERROR] [UHD] Exception caught in safe-call. > in virtual ctrl_iface_impl::~ctrl_iface_impl() > at /home/kurisko/e310/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:76 > this->peek32(0); -> EnvironmentError: IOError: Block ctrl (CE_03_Port_40) > no response packet - AssertionError: bool(buff) > in uint64_t ctrl_iface_impl::wait_for_ack(bool) > at /home/kurisko/e310/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:197 > > terminate called after throwing an instance of 'uhd::lookup_error' > what(): LookupError: Path not found in tree: /mboards/0/tx_dsps/0 > Aborted > root@ettus-e3xx-sg1:~/localinstall/usr/share/uhd/images# > > > For reference, the rfnoc_ce_aut_inst.v file used to create the bitstream > is shown below > > > > localparam NUM_CE = 6; // Must be no more than 14 (2 ports taken by > radio core & PS-PL DMA). > > wire [NUM_CE*64-1:0] ce_flat_o_tdata, ce_flat_i_tdata; > wire [63:0] ce_o_tdata[0:NUM_CE-1], ce_i_tdata[0:NUM_CE-1]; > wire [NUM_CE-1:0] ce_o_tlast, ce_o_tvalid, ce_o_tready, ce_i_tlast, > ce_i_tvalid, ce_i_tready; > wire [63:0] ce_debug[0:NUM_CE-1]; > > // Flattern CE tdata arrays > genvar k; > generate > for (k = 0; k < NUM_CE; k = k + 1) begin > assign ce_o_tdata[k] = ce_flat_o_tdata[k*64+63:k*64]; > assign ce_flat_i_tdata[k*64+63:k*64] = ce_i_tdata[k]; > end > endgenerate > > wire ce_clk = radio_clk; > wire ce_rst = radio_rst; > > noc_block_axi_fifo_loopback inst_noc_block_axi_fifo_loopback ( > .bus_clk(bus_clk), .bus_rst(bus_rst), > .ce_clk(ce_clk), .ce_rst(ce_rst), > .i_tdata(ce_o_tdata[0]), .i_tlast(ce_o_tlast[0]), > .i_tvalid(ce_o_tvalid[0]), .i_tready(ce_o_tready[0]), > .o_tdata(ce_i_tdata[0]), .o_tlast(ce_i_tlast[0]), > .o_tvalid(ce_i_tvalid[0]), .o_tready(ce_i_tready[0]), > .debug(ce_debug[0])); > > noc_block_delay_fifo inst_noc_block_delay_fifo ( > .bus_clk(bus_clk), .bus_rst(bus_rst), > .ce_clk(ce_clk), .ce_rst(ce_rst), > .i_tdata(ce_o_tdata[1]), .i_tlast(ce_o_tlast[1]), > .i_tvalid(ce_o_tvalid[1]), .i_tready(ce_o_tready[1]), > .o_tdata(ce_i_tdata[1]), .o_tlast(ce_i_tlast[1]), > .o_tvalid(ce_i_tvalid[1]), .o_tready(ce_i_tready[1]), > .debug(ce_debug[1])); > > Also this on a fresh install of the most recent UHD rfnoc-devel branch. > No xml was included on this build of it so I have ruled out the xml as > causing the issue. > > Does this mean it may be my user code for the block itself? > I thought, since it is synthesizeable and generates a bitstream, that it > would not be my user code, but I will include the code for my custom block > below. > Does it look like everything is wired up correctly? > > <------------------------------------------------ noc_block_delay_fifo.v > -------------------------------------> > > module noc_block_delay_fifo #( > parameter NOC_ID = 64'hDE7A_0000_0000_0000, > parameter STR_SINK_FIFOSIZE = 11, > parameter MAX_LEN_LOG2 = 16, > parameter WIDTH = 32, > parameter DELAY_VAL = 0) > ( > input bus_clk, input bus_rst, > input ce_clk, input ce_rst, > input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, > output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready, > output [63:0] debug > ); > > //////////////////////////////////////////////////////////// > // > // RFNoC Shell > // > //////////////////////////////////////////////////////////// > wire [31:0] set_data; > wire [7:0] set_addr; > wire set_stb; > reg [63:0] rb_data; > wire [7:0] rb_addr; > > wire [63:0] cmdout_tdata, ackin_tdata; > wire cmdout_tlast, cmdout_tvalid, cmdout_tready, ackin_tlast, > ackin_tvalid, ackin_tready; > > wire [63:0] str_sink_tdata, str_src_tdata; > wire str_sink_tlast, str_sink_tvalid, str_sink_tready, > str_src_tlast, str_src_tvalid, str_src_tready; > > wire [15:0] src_sid; > wire [15:0] next_dst_sid, resp_out_dst_sid; > wire [15:0] resp_in_dst_sid; > > wire clear_tx_seqnum; > > noc_shell #( > .NOC_ID(NOC_ID), > .STR_SINK_FIFOSIZE(STR_SINK_FIFOSIZE)) > noc_shell ( > .bus_clk(bus_clk), .bus_rst(bus_rst), > .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), > .i_tready(i_tready), > .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), > .o_tready(o_tready), > // Computer Engine Clock Domain > .clk(ce_clk), .reset(ce_rst), > // Control Sink > .set_data(set_data), .set_addr(set_addr), .set_stb(set_stb), > .rb_stb(1'b1), .rb_data(rb_data), .rb_addr(rb_addr), > // Control Source > .cmdout_tdata(cmdout_tdata), .cmdout_tlast(cmdout_tlast), > .cmdout_tvalid(cmdout_tvalid), .cmdout_tready(cmdout_tready), > .ackin_tdata(ackin_tdata), .ackin_tlast(ackin_tlast), > .ackin_tvalid(ackin_tvalid), .ackin_tready(ackin_tready), > // Stream Sink > .str_sink_tdata(str_sink_tdata), .str_sink_tlast(str_sink_tlast), > .str_sink_tvalid(str_sink_tvalid), .str_sink_tready(str_sink_tready), > // Stream Source > .str_src_tdata(str_src_tdata), .str_src_tlast(str_src_tlast), > .str_src_tvalid(str_src_tvalid), .str_src_tready(str_src_tready), > // Stream IDs set by host > .src_sid(src_sid), // SID of this block > .next_dst_sid(next_dst_sid), // Next destination SID > .resp_in_dst_sid(resp_in_dst_sid), // Response destination SID for > input stream responses / errors > .resp_out_dst_sid(resp_out_dst_sid), // Response destination SID for > output stream responses / errors > // Misc > .vita_time('d0), .clear_tx_seqnum(clear_tx_seqnum), > .debug(debug)); > > //////////////////////////////////////////////////////////// > // > // AXI Wrapper > // Convert RFNoC Shell interface into AXI stream interface > // > //////////////////////////////////////////////////////////// > wire [31:0] m_axis_data_tdata; > wire m_axis_data_tlast; > wire m_axis_data_tvalid; > wire m_axis_data_tready; > > wire [31:0] s_axis_data_tdata; > wire s_axis_data_tlast; > wire s_axis_data_tvalid; > wire s_axis_data_tready; > > axi_wrapper #( > .SIMPLE_MODE(1)) > axi_wrapper ( > .clk(ce_clk), .reset(ce_rst), > .clear_tx_seqnum(clear_tx_seqnum), > .next_dst(next_dst_sid), > .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), > .i_tdata(str_sink_tdata), .i_tlast(str_sink_tlast), > .i_tvalid(str_sink_tvalid), .i_tready(str_sink_tready), > .o_tdata(str_src_tdata), .o_tlast(str_src_tlast), > .o_tvalid(str_src_tvalid), .o_tready(str_src_tready), > .m_axis_data_tdata(m_axis_data_tdata), > .m_axis_data_tlast(m_axis_data_tlast), > .m_axis_data_tvalid(m_axis_data_tvalid), > .m_axis_data_tready(m_axis_data_tready), > .m_axis_data_tuser(), > .s_axis_data_tdata(s_axis_data_tdata), > .s_axis_data_tlast(s_axis_data_tlast), > .s_axis_data_tvalid(s_axis_data_tvalid), > .s_axis_data_tready(s_axis_data_tready), > .s_axis_data_tuser(), > .m_axis_config_tdata(), > .m_axis_config_tlast(), > .m_axis_config_tvalid(), > .m_axis_config_tready(), > .m_axis_pkt_len_tdata(), > .m_axis_pkt_len_tvalid(), > .m_axis_pkt_len_tready()); > > //////////////////////////////////////////////////////////// > // > // User code > // > //////////////////////////////////////////////////////////// > // NoC Shell registers 0 - 127, > // User register address space starts at 128 > localparam SR_USER_REG_BASE = 128; > > // Control Source Unused > assign cmdout_tdata = 64'd0; > assign cmdout_tlast = 1'b0; > assign cmdout_tvalid = 1'b0; > assign ackin_tready = 1'b1; > > // Settings registers > // > // - The settings register bus is a simple strobed interface. > // - Transactions include both a write and a readback. > // - The write occurs when set_stb is asserted. > // The settings register with the address matching set_addr will > // be loaded with the data on set_data. > // - Readback occurs when rb_stb is asserted. The read back strobe > // must assert at least one clock cycle after set_stb asserts / > // rb_stb is ignored if asserted on the same clock cycle of set_stb. > // Example valid and invalid timing: > // __ __ __ __ > // clk __| |__| |__| |__| |__ > // _____ > // set_stb ___| |________________ > // _____ > // rb_stb _________| |__________ (Valid) > // _____ > // rb_stb _______________| |____ (Valid) > // __________________________ > // rb_stb (Valid if readback data is a > constant) > // _____ > // rb_stb ___| |________________ (Invalid / ignored, same > cycle as set_stb) > // > localparam [7:0] SR_DELAY = SR_USER_REG_BASE; > localparam [7:0] RB_DELAY = 0; > > wire [15:0] delay; > setting_reg #( > .my_addr(SR_DELAY), .awidth(8), .width(16)) > sr_delay ( > .clk(ce_clk), .rst(ce_rst), > .strobe(set_stb), .addr(set_addr), .in(set_data), .out(delay), > .changed()); > > // Readback registers > // rb_stb set to 1'b1 on NoC Shell > always @(posedge ce_clk) begin > case(rb_addr) > RB_DELAY : rb_data <= {32'd0, 16'd0, delay}; > default : rb_data <= 64'h0BADC0DE0BADC0DE; > endcase > end > > //---------------------------------------------------------- > ----------------------------------------- > > //----------------------------------// > // // > // DELAY USER CODE // > // // > //----------------------------------// > > delay_block #(.WIDTH(WIDTH), .MAX_LEN_LOG2(MAX_LEN_LOG2), > .DELAY_VAL(DELAY_VAL)) delay_block1 > ( .clk(ce_clk), .reset(ce_rst), > .delay(delay), > .i_tdata(m_axis_data_tdata), .i_tlast(m_axis_data_tlast), > .i_tvalid(m_axis_data_tvalid), .i_tready(m_axis_data_tready), > .o_tdata(s_axis_data_tdata), .o_tlast(s_axis_data_tlast), > .o_tvalid(s_axis_data_tvalid), .o_tready(s_axis_data_tready)); > > endmodule > > <----------------------------------------------------------- > ------------------------------------------> > > > <----------------------------------------------- delay_block.v > ---------------------------------------------------------> > > > module delay_block > #( parameter WIDTH = 16, > parameter MAX_LEN_LOG2 = 10, > parameter DELAY_VAL = 0) > > ( input clk, input reset, > input [MAX_LEN_LOG2-1:0] delay, > input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output > i_tready, > output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input > o_tready > ); > > reg [15:0] full_count = 3; > wire full = (full_count >= delay) & > new_tvalid; > wire [WIDTH-1:0] new_tdata; > wire new_tlast, > new_tvalid, > new_tready; > > axi_fifo #(.WIDTH(WIDTH+1), .SIZE(MAX_LEN_LOG2)) fifo_delay > ( .clk(clk), .reset(reset), .clear(clear), > .i_tdata({i_tlast, i_tdata}), .i_tvalid(i_tvalid), > .i_tready(i_tready), > .o_tdata({new_tlast, new_tdata}), .o_tvalid(new_tvalid), > .o_tready(new_tready)); > > > > > always @(posedge clk) > begin > if(reset) begin > full_count <= 3; > end > else begin > if(~full & new_tvalid & o_tready) begin > full_count <= full_count + 1; > end > end > end > > assign o_tdata = full ? new_tdata : DELAY_VAL; > assign o_tlast = full ? new_tlast : 1'b0; > assign o_tvalid = full ? new_tvalid : 1'b0; > assign new_tready = full ? o_tready : 1'b0; > > endmodule > > > <----------------------------------------------------------- > -----------------------------------------------> > > > Please let me know what you think. Thanks again. > > > Sincerely, > > Adam Kurisko > > > ------------------------------ > *From:* Adam Kurisko > *Sent:* Wednesday, January 24, 2018 11:26:00 AM > *To:* EJ Kreinar; Martin Braun > *Cc:* USRP-users@lists.ettus.com > > *Subject:* Re: [USRP-users] [RFNoC] uhd_usrp_probe fails and throws > uhd::lookup_error > > > Hi EJ and Martin, > > > Thank you for your responses. > > > Martin: I will try to generate a bitstream without the .xml to see if my > block is at least being recognized as Block_0 and create an xml from that > point. I had made an xml which was used when I generated my error. I used > the fir_filter xml as reference for my blocks xml, but I was suspicious > that it might be the file causing the problem initially. > > > EJ: This is the rfnoc_ce_auto_inst_e310.v that I used when I generated my > error. > > > localparam NUM_CE = 1; > wire [NUM_CE*64-1:0] ce_flat_o_tdata, ce_flat_i_tdata; > wire [63:0] ce_o_tdata[0:NUM_CE-1], ce_i_tdata[0:NUM_CE-1]; > wire [NUM_CE-1:0] ce_o_tlast, ce_o_tvalid, ce_o_tready, ce_i_tlast, > ce_i_tvalid, ce_i_tready; > wire [63:0] ce_debug[0:NUM_CE-1]; > // Flattern CE tdata arrays > genvar k; > generate > for (k = 0; k < NUM_CE; k = k + 1) begin > assign ce_o_tdata[k] = ce_flat_o_tdata[k*64+63:k*64]; > assign ce_flat_i_tdata[k*64+63:k*64] = ce_i_tdata[k]; > end > endgenerate > wire ce_clk = radio_clk; > wire ce_rst = radio_rst; > > noc_block_delay_fifo inst_delay_fifo ( > .bus_clk(bus_clk), .bus_rst(bus_rst), > .ce_clk(ce_clk), .ce_rst(ce_rst), > .i_tdata(ce_o_tdata[0]), .i_tlast(ce_o_tlast[0]), > .i_tvalid(ce_o_tvalid[0]), .i_tready(ce_o_tready[0]), > .o_tdata(ce_i_tdata[0]), .o_tlast(ce_i_tlast[0]), > .o_tvalid(ce_i_tvalid[0]), .o_tready(ce_i_tready[0]), > .debug(ce_debug[0]) > ); > > > Since my initial problem, I have fresh installed UHD and kept the > rfnoc_ce_auto_inst_e310.v and I only modified the last inst of the file > which by default I believe was the fir_filter. This is my current > rfnoc_ce_aut_inst_e310.v file: > > > localparam NUM_CE = 6; // Must be no more than 14 (2 ports taken by > radio core & PS-PL DMA). > > wire [NUM_CE*64-1:0] ce_flat_o_tdata, ce_flat_i_tdata; > wire [63:0] ce_o_tdata[0:NUM_CE-1], ce_i_tdata[0:NUM_CE-1]; > wire [NUM_CE-1:0] ce_o_tlast, ce_o_tvalid, ce_o_tready, ce_i_tlast, > ce_i_tvalid, ce_i_tready; > wire [63:0] ce_debug[0:NUM_CE-1]; > > // Flattern CE tdata arrays > genvar k; > generate > for (k = 0; k < NUM_CE; k = k + 1) begin > assign ce_o_tdata[k] = ce_flat_o_tdata[k*64+63:k*64]; > assign ce_flat_i_tdata[k*64+63:k*64] = ce_i_tdata[k]; > end > endgenerate > > wire ce_clk = radio_clk; > wire ce_rst = radio_rst; > > noc_block_axi_fifo_loopback inst_noc_block_axi_fifo_loopback ( > .bus_clk(bus_clk), .bus_rst(bus_rst), > .ce_clk(ce_clk), .ce_rst(ce_rst), > .i_tdata(ce_o_tdata[0]), .i_tlast(ce_o_tlast[0]), > .i_tvalid(ce_o_tvalid[0]), .i_tready(ce_o_tready[0]), > .o_tdata(ce_i_tdata[0]), .o_tlast(ce_i_tlast[0]), > .o_tvalid(ce_i_tvalid[0]), .o_tready(ce_i_tready[0]), > .debug(ce_debug[0])); > > noc_block_window inst_noc_block_window ( > .bus_clk(bus_clk), .bus_rst(bus_rst), > .ce_clk(ce_clk), .ce_rst(ce_rst), > .i_tdata(ce_o_tdata[1]), .i_tlast(ce_o_tlast[1]), > .i_tvalid(ce_o_tvalid[1]), .i_tready(ce_o_tready[1]), > .o_tdata(ce_i_tdata[1]), .o_tlast(ce_i_tlast[1]), > .o_tvalid(ce_i_tvalid[1]), .o_tready(ce_i_tready[1]), > .debug(ce_debug[1])); > > noc_block_fft inst_noc_block_fft ( > .bus_clk(bus_clk), .bus_rst(bus_rst), > .ce_clk(ce_clk), .ce_rst(ce_rst), > .i_tdata(ce_o_tdata[2]), .i_tlast(ce_o_tlast[2]), > .i_tvalid(ce_o_tvalid[2]), .i_tready(ce_o_tready[2]), > .o_tdata(ce_i_tdata[2]), .o_tlast(ce_i_tlast[2]), > .o_tvalid(ce_i_tvalid[2]), .o_tready(ce_i_tready[2]), > .debug(ce_debug[2])); > > noc_block_fosphor #(.MTU(12) /* Increase output FIFO size to smooth out > bursts */) > inst_noc_block_fosphor ( > .bus_clk(bus_clk), .bus_rst(bus_rst), > .ce_clk(ce_clk), .ce_rst(ce_rst), > .i_tdata(ce_o_tdata[3]), .i_tlast(ce_o_tlast[3]), > .i_tvalid(ce_o_tvalid[3]), .i_tready(ce_o_tready[3]), > .o_tdata(ce_i_tdata[3]), .o_tlast(ce_i_tlast[3]), > .o_tvalid(ce_i_tvalid[3]), .o_tready(ce_i_tready[3]), > .debug(ce_debug[3])); > > noc_block_axi_fifo_loopback inst_axi_fifo_loopback2 ( > .bus_clk(bus_clk), .bus_rst(bus_rst), > .ce_clk(ce_clk), .ce_rst(ce_rst), > .i_tdata(ce_o_tdata[4]), .i_tlast(ce_o_tlast[4]), > .i_tvalid(ce_o_tvalid[4]), .i_tready(ce_o_tready[4]), > .o_tdata(ce_i_tdata[4]), .o_tlast(ce_i_tlast[4]), > .o_tvalid(ce_i_tvalid[4]), .o_tready(ce_i_tready[4]), > .debug(ce_debug[4])); > > noc_block_delay_fifo inst_noc_block_delay_fifo ( > .bus_clk(bus_clk), .bus_rst(bus_rst), > .ce_clk(ce_clk), .ce_rst(ce_rst), > .i_tdata(ce_o_tdata[5]), .i_tlast(ce_o_tlast[5]), > .i_tvalid(ce_o_tvalid[5]), .i_tready(ce_o_tready[5]), > .o_tdata(ce_i_tdata[5]), .o_tlast(ce_i_tlast[5]), > .o_tvalid(ce_i_tvalid[5]), .o_tready(ce_i_tready[5]), > .debug(ce_debug[5])); > > > Thank you again for all your help. I am very close to have my first custom > block up and running and I appreciate you taking the time to help me. > > > Sincerely, > > Adam Kurisko > ------------------------------ > *From:* EJ Kreinar <ejkrei...@gmail.com> > *Sent:* Wednesday, January 24, 2018 6:09:05 AM > *To:* Martin Braun > *Cc:* Adam Kurisko; USRP-users@lists.ettus.com > *Subject:* Re: [USRP-users] [RFNoC] uhd_usrp_probe fails and throws > uhd::lookup_error > > Hi Adam, > > Please copy/paste your rfnoc_ce_auto_inst.v > > In my experience, these errors are usually due to something wrong in this > file. Probably causes are that NUM_CE != the actual number of CEs. Or that > when you added a new CE, you didn't increment the index of the wires, so > two blocks are on the same index. Or, if you've tried to instantiate a DDC > with NUM_CHAN=1, but did not change the NOC_BLOCK_ID to reflect only one > channel > > Of course, could be something else-- those are just the problems I've > personally found (multiple times) that throw similar errors. > > EJ > > > > On Jan 23, 2018 6:18 PM, "Martin Braun via USRP-users" < > usrp-users@lists.ettus.com> wrote: > > On 01/23/2018 03:01 PM, Adam Kurisko wrote: > > I am unsure if I had edited the property subtrees, however I decided to > > fresh install UHD to see if that might fix the problem. I will let you > > know if I experience similar errors. > > > > > > In the mean time while it is installing, could you explain the process > > for implementing the block using UHD without GNU Radio. > > > > > > I have my block made and it simulates/synths/impls in Vivado. > > > > I changed the Makefile.srcs in ..lib/rfnoc to include my custom block. > > > > I changed rfnoc_ce_auto_inst.v in ..top/e300 to instantiate my block. > > > > I run 'make E310_RFNOC' to generate a bitstream. > > > > I then secure copy the generated bitstream into the correct images > > directory on my board > > ...this all looks good... > > > > and finally run 'uhd_usrp_probe' with my custom .bit file. > > ...and this should now list your block. Does it? > > > Does all that seem correct or am I missing a vital step in there > somewhere? > > > > I read in one of your slide shows that I may also need to create a .xml > > file, but is this solely for GNU Radio or do I need to do this for UHD > > as well? > > If you change nothing on the software side, your block will be listed as > "Block_0". You need one XML for UHD and GNU Radio each (so 2 total if > you want to use GNU Radio, but at least 1). > > You can start by literally hacking up an XML file and copying it into > the XML directory, on the E310 it's under > /usr/share/uhd/rfnoc/blocks/*.xml. Also check out our knowledge base > articles on RFNoC block writing. > > Cheers, > Martin > > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > >
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