Hi Tarik, I'm glad you got that working. Yes, modifying UHD is certainly a way that you can specify a custom file. I didn't mention it because the device arguments method works in nearly all software. For instance, the path to the bitstream can certainly be supplied as a parameter in GNU Radio Companion as I said earlier. I've attached a screenshot of the USRP Source block in GRC with an FPGA image specified.
The device arguments are covered in the manual here. http://files.ettus.com/manual/page_configuration.html On Tue, Jan 30, 2018 at 2:34 PM, Tarik Kazaz <t.ka...@tudelft.nl> wrote: > Hello Derek, > > > > I managed to specify custom bistream file by editing one of uhd source > files ( “/rfnoc/src/uhd/host/build/lib/transport/nirio/lvbitx/ > x310_lvbitx.cpp”) > > Changing line 50 to > > std::string fpga_file = “usrp_x310_fpga_RFNOC_” + option + “.lvbitx”; > > > > and then calling in folder “/rfnoc/src/uhd/host/build$” > > > > make > > make install > > > > in order to compile new code. > > > > In this way I redirected path to RFNOC bitstream. > > > > Thank you for your help. > > Indeed I think this is really confusing. Based on documentation, I could > not figure out what is going on. > > I think it would be good to be able to specify path to bit stream as > parameter in gnuradio-companion. > > > > Thank you agin, > > > > Tarik > > > > > > > > > > *From:* Derek Kozel [mailto:derek.ko...@ettus.com] > *Sent:* dinsdag 30 januari 2018 14:33 > > *To:* Tarik Kazaz > *Cc:* Martin Braun; USRP-users@lists.ettus.com > *Subject:* Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images > > > > Hi Tarik, > > The USRP source in GNU Radio has a spot for specifying device arguments. > The osmocom_fft application has a "--args" option the same as the UHD > utilities. There is not currently the ability to specify a custom default > FPGA image but it is a feature we agree would be useful. > > Regards, > > Derek > > > > On Tue, Jan 30, 2018 at 12:24 PM, Tarik Kazaz <t.ka...@tudelft.nl> wrote: > > Hello Derek, > > > > I got you. Thank you. > > > > I have one more question, where can I specify default bit stream location? > > > > What happen now is that by calling > > > > uhd_usrp_probe –args =”fpga=/path/to/image.lvbitx” > > > > I am able to flash USRP with RFNoC design. However, after I run gnuradio > fosphor program it again roles > > back to previous bitstream. Which is logical based on your advices. > > > > However where can I specify path to default bitstream. In which file I > should do it? > > > > Thx for comments related to 10Gbe. Then I think we will need to order also > 10 Gbe interface. > > > > Kind Regards, > > > > Tarik Kazaz > > > > *From:* Derek Kozel [mailto:derek.ko...@ettus.com] > *Sent:* dinsdag 30 januari 2018 11:50 > *To:* Tarik Kazaz > *Cc:* Martin Braun; USRP-users@lists.ettus.com > > > *Subject:* Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images > > > > Hi Tarik, > > Your steps are based on the misunderstanding of how the image loading > occurs in each of these scenarios. > > When using PCIe the FPGA will always be reloaded from the host computer. > Every program you run using the PCIe link needs the > "fpga=/path/to/image.lvbitx" string added to the device arguments. The > image loading is very fast compared to other methods. For example: > > uhd_usrp_probe --args="fpga=/path/to/image.lvbitx" > > When using JTAG an image is loaded into RAM on the FPGA. This will be > overwritten if PCIe is used and forgotten (the RAM will clear) when the > device is turned off. This is useful for rapid testing when using Ethernet > connections since JTAG is faster than writing to flash, and for recovering > when an image with an error has been written to the flash. > > When using the uhd_image_loader the image is written to flash and will be > used the next time the device is turned off and on again. This is useful > for loading a persistent image when using the Ethernet interfaces. PCIe > will still load and use an image from the host every time. > > Can you please try the uhd_usrp_probe with the device arguments specifying > the FPGA image to use? > > As for 2x10 GigE vs PCIe, No, they do not have the same throughput. The > PCIe is equivalent to 1x 10 GigE. In order to get the full bandwidth of the > X3x0, which is 2x 200 MS/s on receive, you would need to use both 10 GigE > connections. > https://kb.ettus.com/X300/X310#Choosing_a_Host_Interface > > Regards, > > Derek > > > > On Tue, Jan 30, 2018 at 10:01 AM, Tarik Kazaz via USRP-users < > usrp-users@lists.ettus.com> wrote: > > Hello Martin, > > I hope I am replying now correctly (I am using reply all to you and > mailing list). > I am still not able to flash RFNoC bit stream on FPGA. Here is what I am > doing: > > 1. First step - Check status of device > > Call: uhd_usrp_probe > Output: [INFO] [X300] Using LVBITX bitfile > /home/cas-sdr/rfnoc/share/uhd/images/usrp_x310_fpga_XG.lvbitx... > ... > | | | RFNoC blocks on this > device: > | | | > | | | * DmaFIFO_0 > | | | * Radio_0 > | | | * Radio_1 > | | | * DDC_0 > | | | * DDC_1 > | | | * DUC_0 > | | | * DUC_1 > > 2. Second step: Load new FPGA image - usrp_x310_fpga_RFNOC_XG.lvbitx: > > Call: uhd_image_loader > --args="type=x300,RESOURCES=RIO0" --fpga-path="/xyz/xyz/rfnoc/ > share/uhd/images > > /usrp_x310_fpga_RFNOC_XG.lvbitx" > > Output: > [INFO] [UHDlinux; GNU C++ version 4.8.4; > Boost_105400; UHD_4.0.0.rfnoc-devel-409-gec9138eb] > [INFO] [NIRIO] rpc_client stopping... > [INFO] [NIRIO] rpc_client stopped. > [INFO] [NIRIO] rpc_client stopping... > [INFO] [NIRIO] rpc_client stopped. > [INFO] [NIRIO] rpc_client stopping... > [INFO] [NIRIO] rpc_client stopped. > [INFO] [NIRIO] rpc_client stopping... > [INFO] [NIRIO] rpc_client stopped. > Unit: USRP X310 (3114FC4, RIO0) > FPGA Image: /xyz/xyz/rfnoc/share/uhd/ > images/usrp_x310_fpga_RFNOC_XG.lvbitx > -- Loading XG FPGA image (this will take > 5-10 minutes)...[INFO] [NIRIO] rpc_client stopping... > [INFO] [NIRIO] rpc_client stopped. > > ....After few minutes I get: > successful. > Power-cycle the USRP X310 to use the new > image. > [INFO] [NIRIO] rpc_client stopping... > [INFO] [NIRIO] rpc_client stopped. > > 3. Third step: power cycle USRP and PC > > Call: sudo /usr/local/bin/niusrprio_pcie stop > Power cycle USRP > Power cycle PC > > > 4. Forth step: power up USRP and PC, check status of USRP > > Call: Power UP USRP > Power UP PC > uhd_usrp_probe > Output: [INFO] [X300] Using LVBITX bitfile > /home/cas-sdr/rfnoc/share/uhd/images/usrp_x310_fpga_XG.lvbitx... > ... > | | | RFNoC blocks on this > device: > | | | > | | | * DmaFIFO_0 > | | | * Radio_0 > | | | * Radio_1 > | | | * DDC_0 > | | | * DDC_1 > | | | * DUC_0 > | | | * DUC_1 > > > So, what I am doing wrong? > > In general I would like to ask you do suggest usage of PCIe or 10GBe > interface with USRP X series? > > In terms of throughput between PC and USRP, PCIe and 2x 10GBe interface > should be same or I am wrong? > > I am asking this because I am working with UWB sampling and compressed > sampling (high throughput is important, especially for Rx side) > My configuration of USRP consists of 2 UBX cards together with X310. > > Maybe I can try to flash usrp_x310_fpga_RFNOC_XG.lvbitx over jtag with > Xilinx tools. However, I do not think .lvbitx is supported with xilinx > tools. > > Thanks once again, > Kind Regards, > Tarik > > > > > > > > > > ________________________________________ > From: Martin Braun [martin.br...@ettus.com] > Sent: Tuesday, January 30, 2018 5:23 AM > To: Tarik Kazaz; 'USRP-users@lists.ettus.com' > > Subject: Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images > > Tarik, > > please remember to keep responses on the mailing list, lest they get lost. > > Yeah, just add fpga=/path/to/image.lvbitx to your device args. > > -- M > > On 01/29/2018 09:56 PM, Tarik Kazaz wrote: > > Hello Martin, > > > > Could you provide me more detailed instruction, how to disable PCIe to > reload image. > > > > I think instead of .bit, I should flash it with .lvbit if I want to use > USRP > > over PCIe with RFNoC? Or I am wrong. > > > > Kind Regards, > > > > Tarik > > > > -----Original Message----- > > From: USRP-users [mailto:usrp-users-boun...@lists.ettus.com] On Behalf > Of Martin Braun via USRP-users > > Sent: maandag 29 januari 2018 20:46 > > To: usrp-users@lists.ettus.com > > Subject: Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images > > > > On 01/29/2018 07:37 PM, Tarik Kazaz via USRP-users wrote: > >> Hello everyone, > >> > >> > >> > >> I am just starting to use RFNoC and I am a bit confused with hardware > >> compatibility for RFNoC development. > >> > >> In order to describe my setup I will list items below: > >> > >> > >> > >> 1. I have NI USRP RIO (equivalent of X310 with integrated GPS > >> module) > >> > >> 2. I am connecting it with PC over PCIe interface > >> > >> > >> > >> I tried to flash USRP with RFNoC *usrp_x310_fpga_RFNOC_XG.bit* image. > >> However, after I power cycle USRP > >> > >> and execute *uhd_usrp_probe* seems that fpga is again flashed with NI > >> USRP as it contains *only DDCs, DMA and Radio* > >> > >> *RFNoC blocks*. > >> > >> > >> > >> In general I am confused what is a right RFNoC image for setup > >> consisting of USRP connected with PC over PCIe interface. > >> > >> Should I *use XG RFNoC FPGA images*? Are RFNoC images compatible with > >> PCIe interface? > > > > Yeah, but PCIe does reload images on every run. If you specify > fpga=/path/to/rfnoc_image.bit, it'll pick that. > > > > > > -- M > > > > _______________________________________________ > > USRP-users mailing list > > USRP-users@lists.ettus.com > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > > >
_______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
