Dear Xingjian, that won't be possible as is – the tuning happens in the AD9361, and the FPGA communicates with that over a serial link. There's timing accuracy requirements that we can't meet over that serial link, so that's why Ettus' AD936x-based device can't support timed commands on the analog tune. If it was easy, we would have done it already!
Best regards, Marcus On Tue, 2018-02-13 at 21:00 +0000, Xingjian Chen via USRP-users wrote: > Hi, > I am interested in controlling LO frequency using E312 in such a way > that timed command must be used. However, as far as I know, E312 > doesn't support timed command for RF front end. So I am thinking if I > could write some simple modules in Verilog HDL setting up LO > frequency. I am wondering if anyone could give me a hint how to > start. What is the best way to program LO center frequency in FPGA > for E312? Thank you. > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
